FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

execute An814

dsun01
New Contributor III
279 Views

Dear Support

 

I have the errors while generate HDL, I am using Quartus PRO 21. 3

I followed the AN814 instruction step by step all the way to Page 11, item 6.b. 

 

Repeat step a. to generate HDL files for jesd204b_ed_qsys.qsys and
dl_count.qsys.

 

 

 

Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_read declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_clk declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_waitrequest declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_avmm_write declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex0 has port reconfig_reset declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex0.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_read declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_clk declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_waitrequest declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_avmm_write declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: jesd204b_subsystem: jesd204b_duplex1 has port reconfig_reset declared with VHDL type standard logic vector which is declared as standard logic in file jesd204b_subsystem_jesd204b_duplex1.ip
Error: The system cannot be generated when there are errors.

0 Kudos
1 Solution
ShengN_Intel
Employee
227 Views

Hi dsun01,

 

Just want to confirm that are you using the manual stated below for guidance?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an814.pdf 

 

If yes, you should use Quartus Prime Pro Edition version 17.0 instead of Quartus PRO 21. 3.

The reference design requires that particular version.

 

Hope it helps.

 

Best regards,
Sheng
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

View solution in original post

3 Replies
ShengN_Intel
Employee
228 Views

Hi dsun01,

 

Just want to confirm that are you using the manual stated below for guidance?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an814.pdf 

 

If yes, you should use Quartus Prime Pro Edition version 17.0 instead of Quartus PRO 21. 3.

The reference design requires that particular version.

 

Hope it helps.

 

Best regards,
Sheng
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

dsun01
New Contributor III
216 Views

Hi Sheng, 

 

Thank you very much for the reply, you answered my question,  I was a little surprised for the application note limited to 17.0.

 

Have a great holiday,

 

David

ShengN_Intel
Employee
211 Views

Hi dsun01,

 

I'm glad that the solution provided could help you.

 

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Have a great holiday too.

 

Best regards,
Sheng


 

Reply