Is there a module or logic files in Verilog/VHDL for passthrough between MAC Wrapper0 and Mac Wrapper1 ?
if no,is there any configue or settings for passthrough between MAC Wrapper0 and Mac Wrapper1?
maybe it already goes through from MAC Wrapper0 to Mac Wrapper1 with the default image for Intel Arria 10GT FPGA ?
Dear JwChin, Figure 13. 8x10G Configuration:https://www.intel.com/content/www/us/en/programmable/documentation/xgz1560360700260.html#met15711656...