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Is there a module or logic files in Verilog/VHDL for passthrough between MAC Wrapper0 and Mac Wrapper1 ?
if no,is there any configue or settings for passthrough between MAC Wrapper0 and Mac Wrapper1?
maybe it already goes through from MAC Wrapper0 to Mac Wrapper1 with the default image for Intel Arria 10GT FPGA ?
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Hi @fzhan51 ,
Thanks for clarifying. Answering to your earlier question, the default factory image is already a passthrough. There is no additional settings required.
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Hi @fzhan51 Could you point me to where is Wrapper 0/1? Which file are you referring to?
When you say passthrough, you mean from the FPGA ingress (from QSFP) to the FPGA egress (to XL710)?
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Dear JwChin, Figure 13. 8x10G Configuration:https://www.intel.com/content/www/us/en/programmable/documentation/xgz1560360700260.html#met1571165665814
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Hi @fzhan51 ,
Thanks for clarifying. Answering to your earlier question, the default factory image is already a passthrough. There is no additional settings required.
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