I've been running through the qsys system design tutorial:
http://www.altera.com/literature/tt/tt_qsys_intro.pdf and have tried putting the design on the board. I ported it over to the Arria II: EP2AGX125EF35C4ES but ran into some problems when trying to connect the pins to DDR3 ram. I followed the pinning for DDR3 in the most straightforward manner (everything looks like it should connect in a 1:1 fashion): http://www.altera.com/literature/manual/rm_aiigx_fpga_dev_board.pdf When I try to compile it gives the following error: Error: I/O standard LVDS_E_3R on input or bidirectional pin sdram_mem_clk_n is not supported by the device at location B12 (PAD_431) -- only output pins of this I/O standard are allowed at this location Error: I/O standard LVDS_E_3R on input or bidirectional pin sdram_mem_clk is not supported by the device at location B13 (PAD_429) -- only output pins of this I/O standard are allowed at this location Those are the only clock signals I can find on DDR3 and so I'm a little lost as to what to do. Does this design only support DDR1?