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4961 Discussions

sharing access to the internal JTAG interface

DMose2
Beginner
157 Views

I'm implementing Encryption in the JTAG secure mode as per AN556 in my design. I want to have access to the internal JTAG interface to be able to unlock / lock the JTAG interface for reprogramming the secure device and I implemented the supplied reference design to do so.

The problem is that the NIOS debug also connects to the internal JTAG and I get a error during synthesis that says the internal JTAG is already connected to the NIOS.

Any idea how I can share this resource between multiple entities?

Thanks!

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6 Replies
MEIYAN_L_Intel
Employee
84 Views

Hi,

May I know the information as below:

  1. OS version
  2. Quartus Prime software edition and version
  3. Device used
  4. Full error message

 

Thanks

DMose2
Beginner
84 Views

1.      OS version – Windows 10 Pro

2.      Quartus Standard Edition version 19.1

3.      Device - 5CEFA7U19I7

4.      Error message:

 

error.JPG

Thanks!

MEIYAN_L_Intel
Employee
84 Views

Hi,

 

Does the design project contains multiple entities (interface JTAG via debug hub and JTAG primitive)?

An additional JTAG primitive will be created in debug hub. But only one JTAG primitive is allowed per device. 

You may need to remove the entities that interface with JATG via debug hub. If the JTAG primitive is part of VQM design, you may need to regenerate VQM file without JTAG primitive. 

 

Thanks

DMose2
Beginner
84 Views

Just wondering ...

Would connecting my JTAG instance via a Virtual JTAG IP core solve this issue?

Dov

DMose2
Beginner
84 Views

haven't heard from you....

The reason I'm asking is because my design already has 2 instances to the internal JTAG:

  1. JTAG UART
  2. NIOS debugger

So, there must be a way to share the internal JTAG with multiple entities.

Do you know of an application note that can help me?

 

Thanks

 

MEIYAN_L_Intel
Employee
84 Views

Hi,

Upon checking, you could be to use jtag interface with multiple entities by set the altera_virtual_jtag to access to the PLD source.

For more information, you may need to refer to the document as link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf

 

Thanks

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