sopc-create-header-files not working for agilex 5

[dasdgw23]

I tried to create header files for agilex 5, but even for the ghrd this failes.

❯ cd altera-ghrd-socfpga/agilex5_soc_devkit_ghrd
❯ sopc-create-header-files qsys_top.qsys --output-dir pd_headers
Could not convert input file /home/dasdgw/agilex_5/altera-ghrd-socfpga/agilex5_soc_devkit_ghrd/qsys_top.qsys to a .swinfo file.
java.lang.RuntimeException: Can't create SopcSystem from invalid EnsembleReport.
at com.altera.tools.sopcformats.sopcinfo2swinfo.SWInfoGeneratorApp$1.publish(SWInfoGeneratorApp.java:117)
at java.util.logging.Logger.log(Logger.java:738)
at java.util.logging.Logger.doLog(Logger.java:765)
at java.util.logging.Logger.log(Logger.java:788)
at com.altera.embeddedsw.utilities.log.model.LoggingModelUtils.logStatus(LoggingModelUtils.java:158)
at com.altera.embeddedsw.utilities.log.model.LoggingModelUtils.logStatus(LoggingModelUtils.java:114)
at com.altera.embeddedsw.swinfo.SopcSystem.create(SopcSystem.java:123)
at com.altera.embeddedsw.swinfo.SopcSystem.createFromSopcinfo(SopcSystem.java:191)
at com.altera.tools.sopcformats.sopcinfo2swinfo.SWInfoGeneratorApp.run(SWInfoGeneratorApp.java:123)
at com.altera.tools.sopcformats.sopcinfo2swinfo.SWInfoGeneratorApp.main(SWInfoGeneratorApp.java:40)
sopc-create-header-files: sopcinfo2swinfo --input=qsys_top.qsys --output=/tmp/sopc-create-header-files.675378.tmp.swinfo failed

[BoonBengT_Altera]

Hi @dasdgw23,

Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.

The sopc-create-header-files seems to be art of the NiosII cli, can you help us to understand more on the platform and example design you are referring to that you are using such as what quartus/nios version, URL of the references design and also which Agilex 5 device you are having that would be great.

Instead of using calling the mention above cli directly, perhaps you can try generating the system first be cli below:

- qsys-generate qsys_top.qsys --synthesis=VHDL --output-directory=./qsys_output

Hope to hear from you soon.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, just checking in to see if there is any further doubts in regards to this matter.

Hope your doubts have been clarified.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB

[dasdgw23]

As you can see in my initial post. It's the ghrd agilex5_soc_devkit_ghrd.

So here is the url to your own ghrd for agilex 5:

https://github.com/altera-opensource/ghrd-socfpga/tree/master/agilex5_soc_devkit_ghrd

And sopc-create-header-files is not only for NiosII
https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForAgilexSoC

Or here, for Arria 10:
https://www.intel.com/content/www/us/en/docs/programmable/683187/20-1/system-memory-map.html

[KennyTan_Altera]

reopening the case

[BoonBengT_Altera]

Hi @dasdgw23,

Noted and thanks for clarifying on the actual example design which you have referred to which is a great help to clarify the situation.

Apologies for the confusion, it seems that using sopc-create-header-files for non-Nios II flows is also present for generating memory maps and headers for HPS devices tree generation.

Hence did you managed to perhaps check with the qsys-generate command mention earlier to ensure valid .sopcinfo is generated?

Please do let us know if there is any observer running through that steps.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Good day, just following up on the previous clarification.

By any chances did you managed to look into it?

Hope to hear from you soon.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, just checking in to see if you managed to check with the qsys-generate command?

Do let us know if you notice further issues.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Since we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. 

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB

[dasdgw23]

I'm still waiting for an explanation how to use sopc-create-header-files for agilex 5.

[KennyTan_Altera]

case reopening

[BoonBengT_Altera]

Hi @dasdgw23,

On your question on how to use the sopc-create-header-files command in the Nios shell, you can refer to the link below for the different options available:

- https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1/generating-header-files-for-host-components.html

Circling back to the error you have earlier did you managed to overcome them? Are you able to run the qsys command to sure the sopcinfo files are generated?

Hope to hear from you soon.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

By any chances did you managed to go through the mention linked above?

And trying out the recommendation steps.

Please do let us know if there is further clarification needed.

Best Wishes

BB

[dasdgw23]

I read the documentation.

Again, please show me a working example for the agilex 5.

[BoonBengT_Altera]

Hi @dasdgw23,

Apologies for the confusion, we have just updated and merge our example design for Agilex 5 devices.

All the design from ghrd, Linux kernel and uboot can be found in the following link below:

- https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/#prebuilt-binaries

Please let us know if there are something else that you are looking for.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, by any chances did you managed to look at the link above?

Just checking in to see if there is any further doubts in regards to this matter.

please do let us know if you have further doubts.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, just checking in to see if there is any further doubts in regards to this matter.

Hope your doubts have been clarified.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dasdgw23,

Greetings, since we do not get any further question on the matter again, hence would assume challenge are overcome. 

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB