we are using Arria 10 SoC FPGA Development Kit Board. generated example design and trying to do Ethernet test (PHY Serial loopback). we are getting CRC errors

[EBERLAZARE_I_Intel]

Hi,

To able to help with your issue can you provide the following:

May I know which Quartus and SoC EDS version you are using?

Which example design you are using?

Also, can you share the CRC errors you are getting?

Are you using Linux environment or baremetal etc? If possible can you share the Uboot log?

[SYadl2]

Hi,

Thank you for the immediate response.

we are using the reference design. the issue was clock settings were not done in clock controller GUI. after doing the correction we were able to get the packets without CRC errors

[EBERLAZARE_I_Intel]

Helo,

Thank you for your prompt update, glad your issue is fix.

If you have further question or any other question, we welcome you to file a new ticket.