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druva1
New Contributor I
285 Views

wrong data in rx_parallel_data A10 Transceiver design

Hi,

I am running a simulation of an Arria 10 native transceiver IP + reset controller IP + Atx_pll

Under the 10GBase Protocol so I can transmit 64 bits of data.

The ref clock is 322.265625 Mhz, sys_clock 100 Mhz

At the moment I am just trying to pass a simple constant value of tx_parallel_data but the rx_parallel_data shows an error.

I am not sure what  I am doing wrong.

 

 

 

 

 

 

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5 Replies
CheePin_C_Intel
Employee
278 Views

Hi,


As I understand it, you are observe incorrect RX parallel data with A10 Native PHY in Modelsim simulation. If I understand it correctly, you are using the Native PHY under 10GBase-R mode. Just would like check with you if you have had a chance to try sending constant sync pattern for 10GBase-R to see if it helps.


Thank you.


druva1
New Contributor I
275 Views

Hi,

Thanks for quickly replying. I am quite new to transcievers.

I've previosly succesfully simulated 1 Channel rx/tx to send 8 bits, by configuration the native with a standard PCS. And setting the Rx word Aligner pattern (hx) to: 17C, with RX word aligner mode to sync_sm. Since I used the 8/10 enconder/ decoder too.

But where could I set up a sync pattern for 10GBase-R in the native PHY IP?

cheers

CheePin_C_Intel
Employee
270 Views

Hi,


For your information, I am not really familiar with the 10GBaseR protocol requirement. However, can you try with the idle pattern of 64'h0707_0707_0707_0707 to see if it helps.


Thank you.


druva1
New Contributor I
252 Views

Hi,

Thanks for the trying to help, the 07070707 didn't help. But I manage to fix my error by synchronizing certain signals.

CheePin_C_Intel
Employee
214 Views

Hi,


Sorry for the delay. Glad to hear that you have managed to resolve the issue.


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