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The following applies to designs with multiple Arria 10 External Memory Interface IPs (EMIF) example designs in the same Quartus Prime project
We will use a DDR4 example design and a QDRIV example design and combine them into a single Qsys which can be used easily to interface with the rest of your design
Renaming the directory and file names will cause less confusion in the long run
When generating an Arria 10 EMIF example design, the folder commonly used to contain the synthesis and simulation Qsys files is named emif_0_example_design
Since both synthesis files are named ed_synth.qsys in each directory we will also rename them for clarity
Give your file/directories new names
We will place ddr4_ed_synth.qsys and qdr4_ed_synth.qsys into a directory named xdr4_example_design
We can now open the Qsys GUI to begin creating our Qsys design
We must ensure the Library under IP Catalog contains our subsystem qsys files
To do this we:
We can now see both qsys subsystems in the Library under System
Qsys Library
Remove any default components like Clock Source if you do not need them
Before we add any new components from the Qsys Library we want to make sure to target an Arria 10 device by clicking View -> Device Family and choosing the Arria 10 device you are using
Arria 10 Device Family
We now add both subsystems to the Qsys design by clicking on ddr4_ed_synth and +Add
Do the same for qdr4_ed_synth
You should end up with a Qsys design similar to this
Let's rename the components for clarity
By exporting some of the ports, we will remove the errors and guarantee that all necessary external signals are routed to the top-level
Here we include
We will save this Qsys design as xdr4.qsys under ../xdr4_example_design and generate the files in that directory as well
Take a look at the reference example generated in Quartus Prime 15.1
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