Arria 10 Multiple EMIF Example Designs in Qsys

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Arria 10 Multiple EMIF Example Designs in Qsys

Arria 10 Multiple EMIF Example Designs in Qsys

The following applies to designs with multiple Arria 10 External Memory Interface IPs (EMIF) example designs in the same Quartus Prime project

• The goal of this document is to show how to integrate two separate Arria 10 example designs into one Qsys design regardless of the memory configuration of the Arria 10 EMIFs
• The memory configurations could be exactly the same or are configured completely different (i.e different memory protocol)

We will use a DDR4 example design and a QDRIV example design and combine them into a single Qsys which can be used easily to interface with the rest of your design

• For simplicity, we are assuming the DDR4 example design and QDRIV example design have been created in different directories
• Please refer to the Arria 10 External Memory Handbook if you do not know how to generate an Arria 10 EMIF example design

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Rename for clarity

Renaming the directory and file names will cause less confusion in the long run 

When generating an Arria 10 EMIF example design, the folder commonly used to contain the synthesis and simulation Qsys files is named emif_0_example_design

• For DDR4, we will rename this directory ddr4_example_design
• For QDRIV, we will rename this directory qdr4_example_design

Since both synthesis files are named ed_synth.qsys in each directory we will also rename them for clarity

• For DDR4, we will change the file name to ddr4_ed_synth.qsys
• For QDRIV, we will change the file name to qdr4_ed_synth.qsys

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Give your file/directories new names

Create XDR4 directory and place contents

We will place ddr4_ed_synth.qsys and qdr4_ed_synth.qsys into a directory named xdr4_example_design

• This is the directory where we will create a new Qsys design that includes these subsystems and where the generated files will reside

Qsys and setting up the Library

We can now open the Qsys GUI to begin creating our Qsys design 

We must ensure the Library under IP Catalog contains our subsystem qsys files 

To do this we:

1. Open Options... under Tool in the Qsys menu
2. Add the xdr4_example_design directory into the IP Search Path and click finish

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We can now see both qsys subsystems in the Library under System

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Qsys Library

Selecting an Arria 10 device & removing unnecessary defaults

Remove any default components like Clock Source if you do not need them 

Before we add any new components from the Qsys Library we want to make sure to target an Arria 10 device by clicking View -> Device Family and choosing the Arria 10 device you are using

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Arria 10 Device Family

Adding Arria 10 EMIF Example Design Qsys Components

We now add both subsystems to the Qsys design by clicking on ddr4_ed_synth and +Add 

Do the same for qdr4_ed_synth 

You should end up with a Qsys design similar to this

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Let's rename the components for clarity

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By exporting some of the ports, we will remove the errors and guarantee that all necessary external signals are routed to the top-level

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Here we include

1. Memory signals that are routed to pins
2. PLL reference clock
3. Global Reset
4. OCT signal which is driven by an RZQ pin

Save the Qsys design and Generate!

We will save this Qsys design as xdr4.qsys under ../xdr4_example_design and generate the files in that directory as well 

Take a look at the reference example generated in Quartus Prime 15.1