CPRI-9.8-COMP-IQMAP-A10

CPRI-9.8-COMP-IQMAP-A10

Introduction

In wireless applications, a fundamental path is the Remote Radio Head (RRH) to Base Station (BTS) path. In the downlink, an analog radio signal is translated into a digital format in which it can then be processed and manipulated. In the uplink direction, the opposite processing is applied. This example design will showcase three of three of the functions that are part of these data paths: compression, mapping of IQ samples into a CPRI Frame, and a CPRI link that carries Control and IQ Payload between the RRH and the BTS. The modules/functions showcased in this design example are part of Altera's solution for wireless applications.

Requirements

Arria 10 PCIe Development Kit
FMC Loopback Card
Quartus II 16.0
Arria 10 PCIe Development Kit ClockControl GUI
Altera_CPRI_IQ_Mapper Tool
CPRI v6 IP License
ModelSim 10.1b or newer version

High-Level Description

A high-level block diagram of the design is shown in Figure 1.0. This design example connects Compression/DeCompression, IQ Mapper/DeMapper, and CPRI IP modules. IQ samples are generated by Linear Feedback Shift Registers (LFSR) and are driven into the Compression Modules. After compression the IQ samples are mapped by the IQ Mapper module and are then driven into the CPRI IP. The CPRI module implements the CPRI protocol. It loads the IQ samples unto the CPRI IQ Data Plane. In this example the CPRI transmit serial link is routed back to the receive serial link, implementing an electrical serial loopback. In the receive direction (uplink), the IQ samples are extracted from the CPRI Frame by the CPRI module and are sent to the IQ DeMapper. From the DeMapper, the IQ samples go to the DeCompression modules. To show the integrity of the IQ data and the impact of compression on the IQ data, this design example uses an Error Vector Magnitude module. The uncompressed IQ Data, generated by the LFSRs, and the De-Compressed IQ Data received in the uplink direction (output of the DeCompression modules) are sent into the EVM module which calculates a difference in magnitude between the two.

Figure 1.0 High-Level Block Diagram

Features

CPRI IP

REC Master
9.8 Gbps
6 AxCs
Direct IQ Mapper Interface

Mapper

9.8 Gbps
6 AxCs
8X Sampling
20MHz LTE

Compression

AxC0 : No Compression
AxC1 : 16:12 Compression
AxC2 : 16:10 Compression
AxC3 : 16:8 Compression
AxC4 : 16:7 Compression
AxC5 : 16:6 Compression

Obtaining the Design

You can obtain the design at the DesignStore. To access the DesignStore, you must have a myAltera account.

Full Design Documentation

The full document can be downloaded using the following link.

File:CPRI-9.8-COMP-IQMAP-A10.pdf

The documentation will provide further details about the design, including.

Setting up the hardware
Running the Design on Hardware
Simulating the Design
Design Modules Details

History

Revision	Date	Comment
1.0	July 2016	Initial Release