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Calculating Channel Loss from DDRx Batch Wizard Results

Calculating Channel Loss from DDRx Batch Wizard Results

About the Channel Loss Calculation Tool

The Channel Loss Calculation Tool helps to analyze the results generated by the HyperLynx DDRx Batch Simulation Wizard when used to simulate external memory interfaces. The input to the tool is the result of Excel files generated by the HyperLynx DDRx Batch Simulation. The output of the tool is the calculated channel loss values needed in the Arria 10 External Memory Interface IP.

Channel Loss Calculation Tool flow.

Channel_Loss_Calculation_Tool_flow.png

c/cd/Channel_Loss_Calculation_Tool_flow.png 

Channel Loss Calculation Example

To use this tool, perform the following steps:

1. Download the Channel Loss Calculation Tool, located below, and place it in the desired directory.

2. Download the DDRx Batch Simulation results, located below, and place it in the desired directory.

3. Open the Channel Loss Calculation Tool and enable macros if prompted.

4. Click on the Import Data button and navigate to the directory where the DDRx Batch Simulation results are stored. Open the DDR_Results<timestamp> folder and click OK. For this example, open the DDR_Results_Jun-9-2015-11h-03m folder and click OK.

5. Click on the Run Program button and enter the memory clock frequency when prompted. For this example, enter 1066MHz and click OK.

NOTE: If an error message appears stating the HyperLynx files could not be found, but the tool is still able to import the data and run - the error message can be ignored.

You should now see the calculated channel loss numbers to be entered in Quartus during the IP generation process.

Calculated channel loss values. 

 

Channel_loss_results.png

e/ef/Channel_loss_results.png

Entering Results in Quartus

To enter these calculated parameters in Quartus for an Arria 10 EMIF IP, click on the Board Timing tab and enter the values into the Intersymbol Interface/Crosstalk section.

Board Timing ISI/Crosstalk parameters for Arria 10 EMIF IP.

Quartus_snapshot.png

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Resource Files

Locate under Board Design and System-Level Timing Closure > Board Simulation > Channel Loss Tool

  • Example: DDRx Batch Simulation results - See Attached

Link to setup Quartus generated IBIS files for use with HyperLynx

https://community.intel.com/t5/FPGA-Wiki/Generating-and-Modifying-IBIS-files-for-Arria-10-EMIF/ta-p/...

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Revision #:
5 of 5
Last update:
‎12-16-2020 04:54 PM
Updated by:
 
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