Changing the D5_Delay value in Quartus post fit to help meet timing on external interfaces
Description
This article is dedicated to Quartus users that need assistance in changing the D5 delay value on a pin to achieve better timing to an external component. Either report DDR timing will show a timing violation or a source synchronous IO may be showing a timing violation to the pin. The D5 delay value can be changed post-fit via an ECO change so that a complete re-compile is not necessary. A post fit compile will change the D5 Delay value to the new setting and perform timing analysis for the new setting.
Changing the D5_Delay value
Using a post-fit compiled design, Pin Planner. Highlight the pin that is not meeting timing as expected to the external component. Source synchronous IO timing violation may be reported on a pin or multiple pins and be obvious which pin is in timing error. Report DDR violations are trickier to identify the pin or set of pins. Refer to this article to identify DDR EMIF pins that are violating timing.
Once the pin has been identified, hover over the pin in pin planner, right click, then “Locate Path -> Locate in Resource Property Editor”
Select the pull down in the “Pad” tab, D5 Delay Chain and select the new value for the D5 Delay.
Close the Resource Property Editor and then from Quartus, go to “View -> Utility Windows Change Manager”.
The following shows a D5 Delay cell being changed from 0 to 1.
Click on the “Check and save all netlist changes” highlighted in red to validate the netlist and then kick off an ECO re-compile. The ECO re-compile will also re-run timing analysis.
If the changes made fix the timing issues, the change manager list can be exported to a tcl file for future use.
The tcl file created can be leveraged to make future changes or add pins that require D5 Delay changes without having to make the changes through the Quartus GUI.
The tcl script can be run from the command line:
quartus_cdb -t <D5_Delay_export_filename>.tcl
An example of an exported tcl file can be found in this article:
Triple Speed Ethernet (TSE) Cyclone V RGMII
