In transceiver GIGE mode, transceiver hard rate match FIFO is performing |I2|(BC50) character deletion/insertion during inter-packet gap and |C2|(BC42) character deletion/ insertion during Auto-Negotiation(AN) process. For further info on how transceiver rate match FIFO perform deletion/insertion in GIGE mode, please refer to Altera Device Handbook Vol.2, Transceiver Functional Modes chapter.
In certain user application, where Altera FPGA is used to a bridge between 2 devices and AN process was not happen at Altera FPGA device as shown in figure below.
User might face the AN link failure between device A and B if have any deletion/insertion happen at Altera FPGA due to PPM difference. Accordingly to IEEE802.3,clause 36, Figure 36-7a-PCS receive state machine diagram,part a, received data at receiver side is consider correct if the data sequence is KDDD, where K= Control character, D= Data as shown in figure below.
However, due to hard rate match FIFO limitation, only 2 byte data,KD (I2(BC50) / C2(BC42)) will be deleted/inserted only. Hence, the 2 byte data deletion/insertion will cause the AN process link failure.
In order to compensate the hard rate match FIFO limitation, Soft Data Handler is design in such the way that it will post-process receiver data and regenerate the correct data sequence of |C1| or |C2|, KDDD.(shown in figure below)