IBIS model IO standard naming nomenclature decoder

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IBIS model IO standard naming nomenclature decoder

Description: This forum article is dedicated to help users know where to find Intel PSG FPGA IBIS models and more easily find the IO standard naming nomenclature decoder.

  • Intel PSG FPGA IBIS models can be found here:


  • Note: Make sure you check the “I have read and accepted the licensing terms and conditions” box to download the list of models, Package RLC Values, and IBIS Model shown in the table.


  • The user guide for each family or the ibs file itself should contain an IO standard naming nomenclature decode section that helps explain each option for our IO standard and associated options.
  • Here is an example from our Arria 10 IBIS Models User Guide found inside the arria10.zip file shown in Table 1. IBIS Models for Intel Devices
All models follow the following naming method:
<I/O Standard>_<I/O>_<Features>
<I/O Standard> refers to:
12 - 1.2V-LVCMOS
15 - 1.5V-LVCMOS
18 - 1.8V-LVCMOS
25 - 2.5V-LVCMOS
lvcmos30 - 3.0V-LVCMOS
lvttl30 - 3.0V-LVTTL
dsstl135i - Differential SSTL-135 Class I
dsstl135ii - Differential SSTL-135 Class II
dsstl125i - Differential SSTL-125 Class I
dsstl125ii - Differential SSTL-125 Class II
dsstl12i - Differential SSTL-12 Class I
dsstl12ii - Differential SSTL-12 Class II
dhstl12i - Differential HSTL-12 Class I
dhstl12ii - Differential HSTL-12 Class II
dhstl15i - Differential HSTL-15 Class I
dhstl15ii - Differential HSTL-15 Class II
dhstl18i - Differential HSTL-18 Class I
dhstl18ii - Differential HSTL-18 Class II
dhsul12 - Differential HSUL-12
dpod12 - Differential POD-12
dsstl12 - Differential SSTL-12
dsstl125 - Differential SSTL-125
dsstl135 - Differential SSTL-135
dsstl15 - Differential SSTL-15
dsstl15i - Differential SSTL-15 Class I
dsstl15ii - Differential SSTL-15 Class II
dsstl18i - Differential SSTL-18 Class I
dsstl18ii - Differential SSTL-18 Class II
hstl12i - HSTL-12 Class I
hstl12ii - HSTL-12 Class II
hstl15i - HSTL-15 Class I
hstl15ii - HSTL-15 Class II
hstl18i - HSTL-18 Class I
hstl18ii - HSTL-18 Class II
hsul12 - HSUL-12
lvds - 1.8V LVDS
lvpecl - 1.8V LVPECL
minilvds - 1.8V mini-LVDS
pod12 - 1.2V POD
rsds - 1.8V RSDS
sstl135i - SSTL-135 Class I
sstl135ii - SSTL-135 Class II
sstl125i - SSTL-125 Class I
sstl125ii - SSTL-125 Class II
sstl12i - SSTL-12 Class I
sstl12ii - SSTL-12 Class II
sstl12 - SSTL-12
sstl125 - SSTL-125
sstl135 - SSTL-135
sstl15 - SSTL-15
sstl15i - SSTL-15 Class I
sstl15ii - SSTL-15 Class II
sstl18i - SSTL-18 Class I
sstl18ii - SSTL-18 Class II

<I/O> refers to:
Column I/O Bank (Begins with Letter 'r'):
rtin - Row input, DIFFIO pin (optional Pin Function)
rtio - Row I/O, DIFFIO pin (optional Pin Function)
rto - Row output, DIFFIO pin (optional Pin Function)

<Features> refers to:
s0 - slow Slew Rate
s1 - fast Slew Rate
d12 - 12mA Current Strength
r25 - 25ohm series on-chip Termination without Calibration
r50c - 50ohm series on-chip Termination with Calibration
g50c - 50ohm parallel on-chip Termination with Calibration
p0 - pre-emphasis disabled
p1 - pre-emphasis enabled
t100 - 100-Ohms Differential OCT
v0 - low VOD
v1 - medium low VOD
v2 - medium high VOD
v3 - high VOD
lv - low voltage (model for non-3V I/O bank supply)
hv - high voltage (model for 3V I/O bank supply)

Example: 12_rtio_d2s1_lv refers to 1.2V LVCMOS I/O standard with 2mA drive strength, and fast slew rate setting on row I/O, differential I/O pins that does not support 3V I/O supply.

Version history
Last update:
‎07-28-2020 02:34 PM
Updated by: