In this lab, all FPGA clocks and resets will be sourced from the HPS. Therefore, you don't need a clock source function in the QSys system.
1. In the QSYs GUI, select the "clk_0" Clock Source, right click, and select "Remove" to delete this function.
Soc_hw_ws_files9.jpg (Click here for image)
2. Now you will add an on-chip RAM to your system and connect it to the high-performance HPS to FPGA bridge AXI interface.
Soc_hw_ws_files10.jpg (Click here for image)
3. In the window which pops up:
Soc_hw_ws_files11.jpg (Click here for image)
4. Now you will add a System ID Peripheral. The System ID Peripheral provides a unique identification number and time stamp to allow SW to verify the version of FPGA hardware being use.
5. The last pre-build peripheral you will add is the workshop validator system. This is the peripheral used by the verification utility to sign the files which verify you've fully completed the workshop.
Soc_hw_ws_files12.jpg (Click here for image)
Now you will create a QSys component based on RTL source code and add that component into your QSys system. The pre-written module provided for the lab uses an Altera Avalon bus interface. When the signals names of a supported bus interface are properly
1. At the bottom left corner of the QSys IP Catalog window, click the "New..." button. This will bring up the QSys "Component Editor" window.
2. In the "Component Type" tab of the "Component Editor" window, make the following changes:
3. In the Component Editor window, click the "Files" tab. In this tab, do the following:
Soc_hw_ws_files13.jpg (Click here for image)
4. Click the "Parameters" tab in the "Component Editor" window. You will see that two parameters "ADDW" and "DATW" have been populated from parameters specified in the file "lab_module.sv".
5. Click the "Signals & Interfaces" tab in the Component Editor window. You will see that the clock, reset, and Avalon Memory Mapped Slave interface have all been populated by analyzing the IO in the source file. However, the Component Editor has not associated the AV-MM Slave with the reset input.
You have now built a custom QSys component which can be instantiated in your system.
Soc_hw_ws_files14.jpg (Click here for image)
6. Finally, you will instantiate your new component. In the IP Catalog window, under "Project", expand "Lab Components", select "Lab Module", click the "Add..." button, then clock "Finish" in the Lab Module component window. You system should now look like this.
Soc_hw_ws_files15.jpg (Click here for image)
Next you will connect the clocks and resets for your QSys system. In this lab, we will connect all interfaces to the 50MHz h2f_user1_clock. In areas of a system where performance is important, you would likely run the high performance HPS to FPGA, FPGA to FPGA, and FPGA to SDRAM bridges at a higher clock frequency and run only the lightweight HPS to FPGA bridge at slower clock rate. However, for the purposes of this lab, 50MHz for the system will suffice.
1. In the QSys "System Contents" tab, under the "hps_0" component, select the "h2f_user1_clock" signal. This will highlight it's connection to the rest of the system.
2. For all of the "Clock Input" signals on all of the components, including "hps_0", use the pointer to enable the connection by clicking the empty circle where the h2f_user1_clock" signal intersects each "Clock Input" signal, as show below.
Note: there will be delay between when you click and when the connection appears.
Soc_hw_ws_files16.jpg (Click here for image)
3. Under the "hps_0" component, select the "h2f_reset" Reset Output signal, then connect this signal to the "Reset Input" signals of the four slave components.
Soc_hw_ws_files17.jpg (Click here for image)
You will connect the HPS AXI bridge masters to the Avalon-MM ports of the FPGA slaves. As the QSys fabric will automatically translate between supported memory mapped bus standards, no AXI to Avalon bridges are required.
1. Connect the On-Chip RAM to the HPS-to-FPGA high performance bridge.
2. Connect the HPS to FPGA Lightweight bridge to the other three components in the system.
Soc_hw_ws_files18.jpg (Click here for image)
3. Now you will set the base addresses for the FPGA peripherals. These base addresses are the offsets from the address of the HPS/FPGA bridge to which the peripherals are attached. Set the following addresses by double clicking on the address in the "Base" column next to each perpheral in the "System Contents" window.
Be certain that these addresses are correct. If they are not, the pre-compiled validator component won't function properly.
Soc_hw_ws_files19.jpg (Click here for image)
Finally, you wil export the HPS peripheral IO from the QSys system.
1. In the QSys "System Contents" window, under "hps_0", find the "memory" conduit. In the "Export" column, double click on "Double-click to export" in the "memory" conduit row. The exported interface name should show up as "memory".
2. In the QSys "System Contents" window, under "hps_0", find the "hps_io" conduit. In the "Export" column, double click on "Double-click to export" in the "memory" conduit row. Change the name of the exported interface to "hps_0_hps_io".
It is important that these names are correct as these names are used in the top-level module for the project.
Your final QSys system should look like this:
Soc_hw_ws_files20.jpg (Click here for image)
1. From the QSys "Generate" menu, select "Generate HDL..."
2. In the "Generation" dialog box, keep the default. The project as implemented uses Verilog. For your own custom designs, you can select either Verilog or VHDL.
3. Click the "Generate" button.
4. When generation is complete, click the "Close" button and continue with the next section of the lab.
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