Click on the "Generation" tab at the top of the Qsys screen. A screen similiar to Figure 1-4 should appear. For the Simulation settings, choose the HDL language you prefer, and choose Standard BFM's... for the Create Testbench Qsys system option. Choose an output directory (your project directory) and click generate at the bottom of the screen.
After the design files have been generated, open ModelSim. Navigate to <project_dir>/testbench/mentor. type "source msim_setup.tcl". This will prepare the .Tcl script that will compile your design. use a combination of the options given to compile the design, or just type "ld_debug" for a full compilation. A screen similiar to Figure 1-5 will appear.
After compilation has completed, add any signals you would like to the wave window, and type "run -all" to run the simulation in its entirety. See Figure 1-6 for an example of how the ModelSim screens should appear after compilation completes.