Stratix V Hard IP For PCI Express Instantiation Walkthrough

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Stratix V Hard IP For PCI Express Instantiation Walkthrough

Stratix V Hard IP For PCI Express Instantiation Walkthrough



This article serves to guide the user through the process of using Quartus II (Qsys), and Modelsim to generate, compile, and simulate the Altera provided PCIe Hard IP design files.

Required Materials


  1. Create a folder to serve as your project directory. This project uses C:\Sandbox\ 
  2. Open Quartus II. Then click on the Qsys icon at the top menu bar of the Quartus II main screen. See Figure 1-1.
  3. Figure 1-1: Quartus II Main Screen /a/ac/Qaurtus_main_screen.png
  4. Once Qsys opens, go to File > Open. See Figure 1-2. Then navigate to <quartus_installation_directory>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/sv
  5. and then select the PCIe configuration you would like to instantiate. 
  6. Figure 1-2: Default Main Screen for Qsys 4/43/Qsys_Open.png
  7. After you have selected your configuration, a new screenw ill appear similiar to figure 1-3
  8. Figure 1-3: Qsys Main Screen After Configuration Is Selected
    1. qsys-main-screen
  9. Click on the "Generation" tab at the top of the Qsys screen. A screen similiar to Figure 1-4 should appear. For the Simulation settings, choose the HDL language you prefer, and choose Standard BFM's... for the Create Testbench Qsys system option. Choose an output directory (your project directory) and click generate at the bottom of the screen. 
  10. Figure 1-4: Qsys Generation Tab 3/32/Qsys_generation.png
  11. After the design files have been generated, open ModelSim. Navigate to <project_dir>/testbench/mentor. type "source msim_setup.tcl". This will prepare the .Tcl script that will compile your design. use a combination of the options given to compile the design, or just type "ld_debug" for a full compilation. A screen similiar to Figure 1-5 will appear. 
  12. Figure 1-5: ModelSim Main Screen
    1. modelsim-main-screen
  13. After compilation has completed, add any signals you would like to the wave window, and type "run -all" to run the simulation in its entirety. See Figure 1-6 for an example of how the ModelSim screens should appear after compilation completes. 
  14. Figure 1-6: Main Screen After Compilation Completes 7/71/Modelsim_run_all.png



More Detailed Simulation Readouts 

This short article guides the user through instantiating design files that give the user control over how detailed they want the simulation readouts to be, from very detailed, to not so detailed.


© 2011 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

Key Words

PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files, Hard, IP, 

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Last update:
‎12-27-2022 03:37 PM
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