This article serves to guide the reader through the steps taken to design, compile, simulate, and port to hardware the reference transceiver design (Native PHY IP) included in this article, using a Stratix V FPGA. This guide should be used as a reference for those wanting to create a transceiver design from scratch- using MegaWizard and user generated design files to form a complete design. The completed reference project archive is available for download through this article.
To create a transceiver design from scratch, you must first generate the Transceiver PHY IP and a Reconfiguration Controller as well as a Reset Controller. All are generated by using the MegaWizard. The user should understand exactly which Transceiver PHY IP they will need. This depends on the protocol being implemented. Refer to the table above in the "Supported Protocols" section, as well as to the Altera Transceiver PHY IP Core User Guide and the Transceiver Configurations in Stratix V Devices documentation.
The MegaWizard will allow you to easily generate the Transceiver PHY IP, the Transceiver Reconfiguration Controller, and the Reset Controller. Refer to the Altera Transceiver PHY IP Core User Guide , or Level 2 articles in the Transceiver Design Flow Series for more information about the IP.
A screen similiar to Figure 3-1 will appear after completing step #1. Here you can edit parameters for the PHY IP to suit your design requirements. For details about the configurable settings for each PHY IP, see the Altera Transceiver PHY IP Core User Guide "Parameter Settings" sub-section of each protocol section. When finished, click "Finish."
Repeat Steps 1-3 for the Reconfiguration Controller. You may also need to repeat Steps 1-3 for an external Reset Controller, depending on the Transceiver PHY IP that you are implementing. For this article, we are implementing a Native PHY IP, which does require an external reset controller. To find out whether or not you need to instantiate your own Reset Controller, refer to the chapter that pertains to the Transceiver PHY IP you are implementing within the Altera Transceiver PHY IP Core User Guide .
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