How to control Tiger Lake DSC on Windows 10 x 64

[Toby4]

I want to control Tiger Lake DSC on Windows 10 x 64.

When I searched, I found open source graphics data on the Linux site.

https://01.org/node/37295

intel-gfx-prm-osrc-tgl-vol-02-c-command-reference-registers-part-1.pdf
intel-gfx-prm-osrc-tgl-vol-02-c-command-reference-registers-part-2.pdf

Can I change the DSC register to control the DSC in Windows?

[Jean_Intel]

Hello Toby4,

Thank you for posting on the Intel️® communities.

I will proceed to check the issue internally and post back soon with more details.

Best regards,

Jean O. 

Intel Customer Support Technician

[Toby4]

DP 1.4 is used on the DSC monitor to automatically capture 144HZ in the window.
I want to know if the attached address value can be controlled by C++.

[MUC]

I'm referring to DSC via HDMI 2.1 FRL.

For the absolute expert who dares to experiment, there is that. This tool creates software EDID overrides in the Windows registry. So graphics adapters can be forced to specific resolutions and other parameters.

Parameters for DSC are contained in the CTA-861 Extension Block for "HDMI Forum Vendor Specific" and cover the following being enabled/disabled or specified (last 3 ones):

• main flag to enable DSC
• 10 bpc
• 12 bpc
• 16 bpc
• 1p2 (1.2V electrical voltage)
• All bpp
• DSC native YCbCr 4:2:0
• maximum FRL Rate (one of the following options which means Gbps per lane)
  • no support for compressed video transport
  • 3 Gbps
  • 6 Gbps 3 lanes
  • 6 Gbps 4 lanes
  • 8 Gbps
  • 10 Gbps
  • 12 Gbps
• maximum slices (one of the following options)
  • VESA DSC 1.2a is not supported
  • up to 1 slice and up to (340 MHz/KSliceAdjust) pixel clock per slice
  • up to 2 slices and up to (340 MHz/KSliceAdjust) pixel clock per slice
  • up to 4 slices and up to (340 MHz/KSliceAdjust) pixel clock per slice
  • up to 8 slices and up to (340 MHz/KSliceAdjust) pixel clock per slice
  • up to 8 slices and up to (400 MHz/KSliceAdjust) pixel clock per slice
  • up to 12 slices and up to (400 MHz/KSliceAdjust) pixel clock per slice
  • up to 16 slices and up to (400 MHz/KSliceAdjust) pixel clock per slice
• maximum total chunk [kilobytes] 

On my test device NUC11TNKv7 Win 11 22H2 operating Intel Iris Xe (Tiger Lake-UP3 - GT2) it was necessary to provide the flag for “All bpp”, otherwise there was no DSC. Please also note this: https://www.dell.com/support/kbdoc/en-us/000197102/how-to-enable-display-stream-compression-on-latitude-precision-and-xps

This is the configuration for the e-ShiftX 8K Home Cinema Projector JVC DLA-NZ8 operated through a 40 Gbps AV-Receiver.

For the sake of completeness be aware that if DSC is once enabled (basic capability of the source like in link above and EDID authorized by display) it may also be used for signal transmission that actually wouldn’t require DSC and could also be transmitted uncompressed.

[Toby4]

DP 1.4 is used on the DSC monitor to automatically capture 144HZ in the window.
I want to know if the attached address value can be controlled by C++.

[Jean_Intel]

Hello Toby4,

We appreciate your patience.

As per the article "Is Display Stream Compression (DSC) Supported on My Intel® Graphics?", we can confirm that DSC is supported starting with 11th Generation Intel® Core Processor Graphics (also known as Tiger Lake) and newer.

However configuration and modifying registry keys are not something we do provide support for, you should contact your system manufacturer (OEM) for assistance on configuration.

Best regards,

Jean O.

Intel Customer Support Technician

[Jean_Intel]

Hello Toby4,

We hope you are doing fine.

We have not heard back from you. So we will close this thread. If you need any additional information, submit a new question, as this thread will no longer be monitored.

Best regards.

Jean O. 

Intel Customer Support Technician.