intel AMT & Nehalem

marten_gajda · ‎03-27-2009

hello,

the following article mentions that with intel AMT enabled chipsets there is a micro-controller within the graphics and memory controller hub:

http://software.intel.com/en-us/articles/architecture-guide-intel-active-management-technology/

With Nehalem architecture the memory controller is moved into the cpu.
What about the AMT micro-controller?
Do Nehalem cpus feature an additional micro controller for AMT?

Thank you,

regards

Marten Gajda

Lance_A_Intel · ‎03-27-2009

Hello Marten,
This is a good question. I have not seen any material on this yet and will need to investigate what information is publicaly available.

You may be interested in looking at the Overview document within the DOCS folder of our latest SDK which has AMT architecture information for previous thorugh current releases.

Gael_H_Intel · ‎03-30-2009

Quoting - marten.gajda

hello,

the following article mentions that with intel AMT enabled chipsets there is a micro-controller within the graphics and memory controller hub:

http://software.intel.com/en-us/articles/architecture-guide-intel-active-management-technology/

With Nehalem architecture the memory controller is moved into the cpu.
What about the AMT micro-controller?
Do Nehalem cpus feature an additional micro controller for AMT?

Thank you,

regards

Marten Gajda

Hi Marten - sorry it's taken a while to get back with you. As "Nehalem" and Intel AMT are concerned we don't have a bunch of publicy available information yet. I did find a link, however (not on an intel site!) it has this picture of the architecture. This may be the closest we can get to finding you an answer. Check out the links and let us know if it helps.

marten_gajda · ‎03-30-2009

Quoting - Gael Holmes (Intel)

Hi Marten - sorry it's taken a while to get back with you. As "Nehalem" and Intel AMT are concerned we don't have a bunch of publicy available information yet. I did find a link, however (not on an intel site!) it has this picture of the architecture. This may be the closest we can get to finding you an answer. Check out the links and let us know if it helps.

Hi Gael,
thank you. I think this picture answers my question in the first place.
It seems reasonable to put the Management Engine into the IO-Hub. But I'm curios how the ME can access the system memory when the system is in powered-off or S3 state. Maybe I did not quite understand if the ME does access the systems RAM in powered-off state at all (I'm pretty sure it does to provide the "powered-off services"). The Architecture Guide mentions S3 only.
I can think of two possible solutions (both seem somewhat unlikely to me)
1) the ME can enable the cpu's memory controller for short time periods in S3 and even powered-off state
2) the ME features it's own RAM
Marten

Gael_H_Intel · ‎03-30-2009

Quoting - marten.gajda

Hi Gael,
thank you. I think this picture answers my question in the first place.
It seems reasonable to put the Management Engine into the IO-Hub. But I'm curios how the ME can access the system memory when the system is in powered-off or S3 state. Maybe I did not quite understand if the ME does access the systems RAM in powered-off state at all (I'm pretty sure it does to provide the "powered-off services"). The Architecture Guide mentions S3 only.
I can think of two possible solutions (both seem somewhat unlikely to me)
1) the ME can enable the cpu's memory controller for short time periods in S3 and even powered-off state
2) the ME features it's own RAM
Marten

Hi Marten,
You have very good questions. Unfortunately since the AMT product has not launched and is not available for public consumption, we cannot answer your questions at this time. We will put the architectural information up on the community as soon as it is available to do so.

Thanks!

marten_gajda · ‎03-31-2009

Quoting - Gael Holmes (Intel)

Hi Marten,
You have very good questions. Unfortunately since the AMT product has not launched and is not available for public consumption, we cannot answer your questions at this time. We will put the architectural information up on the community as soon as it is available to do so.

Thanks!

ok, I understand.
Thank you!