It is possible to decrease compilation time on fpga_compile node more then 3 times.
During compilation aoc make a lot of read/writes on project and tmp folders. Usually these folders are on users login virtual machine and compile node are on separate computer in cluster. These operations is quite slow. But there is temporary folder resides on compile node which can be used locally on node and which can help to avoid a lot of transfers through nfs. This folder is being created for each job on a node and is being deleted after job finished. You can find it in $PBS_SCRATCHDIR
So, simple script to use this feature (for "vector add" example) is:
#!/bin/bash date source /opt/intel/inteloneapi/setvars.sh xTMPDIR=$TMPDIR export TMPDIR=$PBS_SCRATCHDIR/tmp U_SRC_DIR=$PWD cd $PBS_SCRATCHDIR mkdir tmp cp -rf $U_SRC_DIR/* . CPU_QTY=`nproc` echo "Number of CPUs: $CPU_QTY" make -j $CPU_QTY hw -f Makefile.fpga cp -rf $PBS_SCRATCHDIR/tmp $xTMPDIR rm -Rf $PBS_SCRATCHDIR/tmp cp -rf $PBS_SCRATCHDIR $U_SRC_DIR export TMPDIR=$xTMPDIR cd $U_SRC_DIR date exit 0
to run this script on compile node:
qsub -l nodes=1:fpga_compile:ppn=2,walltime=24:00:00 -d . build_fpga_hw.sh
Instead of more than 4 hours it takes 1.2 hour.
Thanks for the information you shared.If you face any issues regarding FPGA,you may post your queries in FPGA forum:(https://forums.intel.com/s/topic/0TO0P0000001AUUWA2/intel-high-level-design?language=en_US)