Unable to submit job to fpga_compile nodes

[Wes]

I am trying to run a compilation job targeting a Stratix 10 on the DevCloud using one of the `fpga_compile` nodes. 

The command I am using to submit the job is this:

 qsub -q batch@v-qsvr-fpga -l nodes=1:fpga_compile:ppn=2 <script_name>

 The error output I get is this: 

qsub: submit error (Job exceeds queue resource limits MSG=cannot locate feasible nodes (nodes file is empty, all systems are busy, or no nodes have the requested feature))

Process exceeded login node resource limit.
Please run jobs on compute nodes using qsub or start an interactive shell using qsub -I.
Please visit the forums at: https://software.intel.com/en-us/forums/intel-devcloud

Additionally, If I try to run compilation manually, using an interactive job using the following command, I am unable to run the compilation because the `afu_synth_setup` script/tool is not available. Am I misinterpreting the purpose of the `fpga_compile` nodes? Are they not actually for FPGA (Stratix 10/Arria 10) compilation?

qsub -l nodes=1:fpga_compile:ppn=2 -I

[JaideepK_Intel]

Hi,

Thank you for posting in Intel Communities.

The command you used to access FPGA compile nodes is not correct.

qsub -q batch@v-qsvr-fpga -l nodes=1:fpga_compile:ppn=2 <script_name>

-q batch@v-qsv : Basically, this option is to enable FPGA OpenCL nodes, but on the OpenCL queue there are no FPGA compile nodes available, so you are getting the above error.

Simply run the following command to get access to fpga compile nodes. 

qsub -l nodes=1:fpga_compile:ppn=2 <script_name>

For more information

Please see the link below for more information:

https://github.com/intel/FPGA-Devcloud/blob/master/main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Arria10/README.md

There are currently some licensing issues for FPGA nodes, which could be the source of this problem. 

To understand your issue further please provide exact steps to reproduce your issue.

Thanks,

Jaideep

[Wes]

Thanks for the reply. After I am logged into an fpga_compile node (using the command you provided, but adding the `-I` interactive flag), I cannot actually use the `afu_synth_setup` script to initialize a compilation directory.

Here are the steps I am taking: 

# Login to an fpga_compile node interactively.
qsub -l nodes=1:fpga_compile:ppn=2 -I

# Source the login setup script
source /data/intel_fpga/devcloudLoginToolSetup.sh

# Run the tools_setup script, choosing Stratix 10 Dev Stack option
tools_setup -t S10DS

After these steps, I would expect to be able to run the `afu_synth_setup` script as shown in this step of the guide you linked above: https://github.com/intel/FPGA-Devcloud/blob/master/main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Arria10/README.md#32-compiling-rtl-code-into-an-fpga-bitstream

However, I get a "command not found" error. Are these the wrong nodes for this task?

[JaideepK_Intel]

Hi,

Please follow the below steps:

Change to FPGA queue with the below command.

export PBS_DEFAULT=v-qsvr-fpga
source /data/intel_fpga/devcloudLoginToolSetup.sh .

To login FPGA nodes use the below command.

devcloud_login

>>Select option 3 or option 5 and connect to a Stratix 10 ready compute node.

After login inside the node try to source the below command once again.

source /data/intel_fpga/devcloudLoginToolSetup.sh .
tools_setup

After running the above commands, you can follow the documentation below.

Link:

FPGA-Devcloud/main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Stratix10 at master · intel/FPGA-Devcloud · GitHub

Compiling looks like below:

If this resolves your issue, make sure to accept this as a solution. This would help others with similar issue. Thank you!

Regards,

Jaideep

[JaideepK_Intel]

Hi,

If this resolves your issue, make sure to accept this as a solution. This would help others with similar issue. Thank you!

Thanks,

Jaideep

[JaideepK_Intel]

Hi,

Good day to you.

We assume that your issue is resolved. If you need any additional information, please post a new question as this thread will no longer be monitored by Intel.

Thanks,

Jaideep,