Sparsity support on Myriad X

[l__tim]

I see some demo models with sparse/pruned variants available but no mention of sparsity support in the documentation. Is or will sparsity be supported on the Myriad X and what benefits can be expected ?

[Munesh_Intel]

Hi Tim,

Intel® Movidius Myriad™ X features 16 programmable Very Long Instruction Word (VLIW)  vector processors, called Streaming Hybrid Architecture Vector Engine (SHAVE) cores, to accelerate neural networks by performing workloads in parallel. 

The SHAVE cores provide full support for sparse data structures (matrix/array, random access). Thus, they can complement the Neural Compute Engine by running custom layer types for Convolutional Neural Network (CNN) applications.

With regards to sparse data acceleration, the SHAVE cores support sparse data operations with the load-store unit (LSU) using eight 4-bit fields to generate the address.

More information is available at the following pages:

https://www.intel.com/content/www/us/en/products/processors/movidius-vpu/movidius-myriad-x.html

https://en.wikichip.org/wiki/movidius/microarchitectures/shave_v2.0#Architecture

https://en.wikichip.org/wiki/movidius/microarchitectures/shave_v2.0#Sparse_Data_Acceleration

Regards,

Munesh