Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
884 Discussions

Cyclone IV Configuration. nStatus staying low, IO pins driving low on power-up.

MHolm8
Beginner
443 Views

In our application, we have an FPGA with a Nios processor programming a second (downstream) FPGA in Passive Serial mode. I've recently redesigned this downstream board and am finding that the downstream board is unable to configure, given that the nStatus pin is never released by the downstream board.

 

The downstream FPGA is a cyclone IV E series 144 pin qfp EP4ce22e22c7n.

 

Furthermore, I know that at least one IO pin is not tri-stated on power up, but driving low with an impedance of 300 ohms.

 

Visual inspection shows that all FPGA pins are well-soldered. The 1.2V VCCInt and VCCD_PLL rails and 2.5V VCCIO and VCCA rails are at appropriate and stable voltages. The newest rev board's power connections to the FPGA are identical to the working older rev's, and the FPGA isn't soldered on backwards or anything like that.

 

The problem persisted when the FPGA was desoldered and a new chip was soldered in its place.

 

Does anyone have an idea as to what could cause these symptoms?

0 Kudos
1 Reply
HBhat2
New Contributor II
208 Views

Hi,

 

nStatus is open drain IO. It will be floating if no external pull up is provided.

 

With Regards,

HPB

Reply