Greetings to all Qsim Intel FPGA starter users,
I use that version for UVM interview preparation. And I tried to compile the uvm-UVM_1_2_RELEASE/distrib/examples/integrated/codec and run the example however it requires svverification license with no debug message.
The error is as follows, I would like to check whether it's practical to use this tool for my study?
Thank you!
Qs user
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found.
# This also means that later if you turn on UVM-aware debugging your debug simulations may have
# different random seeds from your non-debug simulations.
# Loading sv_std.std
# Loading work.vip_if(fast)
# Loading work.vip_tx_if(fast)
# Loading work.vip_rx_if(fast)
# Loading work.apb_if(fast)
# Loading work.tb_ctl_if(fast)
# Loading work.uvm_pkg(fast)
# Loading work.vip_pkg(fast)
# Loading work.apb_pkg(fast)
# Loading work.uvm_sv_unit(fast)
# Loading work.tb_top(fast)
# ** Error: Failure to checkout svverification license feature.
# Error loading design
Error loading design
# End time: 17:49:51 on Mar 06,2024, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
make: *** [Makefile:34: run] Error 12
