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808 Discussions

How to specify a path to the executables of the ModelSim-Altera software?

PSriv8
Novice
2,806 Views

I have compiled a project in Altera and want to simulate the same using ModelSim-Altera software. I have already selected the ModelSim as a default simulator in the project setting so that it can simulate the design after compilation. However, the compilation stops at 83% as it is not able to simulate the project. I tried to simulate it manually but this message appears:

 

Quartus.PNG

 

Would anyone suggest how to resolve this?

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1 Solution
RichardTanSY_Intel
2,708 Views

Go to Tools > Options > EDA Tool Options.

Check that the path to the ModelSim-Altera software is correctly set to: <install_directory>\win32aloem (for example, C:\intelFPGA\18.1\modelsim_ae\win32aloem)

Capture.JPG

 

p.s. Don’t forget to Reply, and Select the Best Solution. :)

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4 Replies
RichardTanSY_Intel
2,709 Views

Go to Tools > Options > EDA Tool Options.

Check that the path to the ModelSim-Altera software is correctly set to: <install_directory>\win32aloem (for example, C:\intelFPGA\18.1\modelsim_ae\win32aloem)

Capture.JPG

 

p.s. Don’t forget to Reply, and Select the Best Solution. :)

PSriv8
Novice
2,708 Views

Thank you so much for the solution, now the modelsim is accessible automatically. However, I am not able to view the waveform. Do I need to add the variables to view waveform. Also, would you please tell me the difference between RTL simulation and Gate Level Simulation? I am sorry if my questions are very basic, I am a beginner therefore having many doubts.

RichardTanSY_Intel
2,708 Views

You might need to provide further detail on why you are not able to view the waveform. Try to go through an example design/online tutorial to check where goes wrong.

 

RTL simulation is to check the design functionality without taking into account the delays of the lookup tables. Gate level simulation can also be zero delays but is more often used in unit delay or full timing mode. 

Post-synthesis and post-fit gate-level simulations run significantly slower than RTL simulation. Intel FPGA recommends that you verify your design using RTL simulation for functionality and use the Timing analyzer for timing.

You can learn more about simulation from the link below:

https://www.intel.com/content/www/us/en/programmable/documentation/gft1513990268888.html

 

PSriv8
Novice
2,708 Views

Thank you for your reply. It helped a lot.

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