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Nativelink fails simulating altera_gpio_lite for MAX10 in Quartus 18.1.1 Lite

BAdam1
Beginner
467 Views

# vlog -vlog01compat -work work +incdir+C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA {C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo}

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016

# Start time: 11:16:55 on Aug 09,2019

# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA" C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo 

# ** Error: (vlog-7) Failed to open design unit file "C:/src/FPGA_ENG/trunk/Project9_Porter/SUM_FPGA/GPIO_bi.vo" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 11:16:55 on Aug 09,2019, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

 

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1 Reply
RichardTanSY_Intel
211 Views
Could you help to share the design so I could troubleshoot the error?
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