Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
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Nios processor fails on reset occasionally.


I have a Nios II processor operating on a Cyclone V device. I have found that maybe 5% of the time it comes up in a weird state. Shortly into execution after reset, the processor branches to 0x0. I can tell if it's branching to zero or the reset vector because they are the same. It only does this on a call instruction and it happens ~ 26 us after release from reset. It doesn't always happen on the same call instruction, but so far it has always been a call instruction. I used signal tap to track the execution to determine where it fails. I examined the instruction read data register to verify that the correct opcode was being read into the processor. The last instruction read is a proper call opcode (executing from flash with cache, cache never gets re-used in this scenario). The processor then does a burst read of SRAM and the next opcode is read from address zero (reset vector). Anybody ever seen anything like this? Additional information: If you reset the processor internally it happens mush more often. Currently we are performing a system reset which is reloading the FPGA from the prom. It doesn't seem to make a difference if it's a power-on or an FPGA re-load. None of the reset signals are active while the processor is stuck in this loop. It never exits this loop. It keeps restarting execution at zero. There are no external forces at work on the processor during this time. Cycle power and it goes away. Is it possible there is some power-on sequencing that's missed?


Any help is appreciated,



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Hello CBehr Thank you for posting in the Intel Community. I am moving you thread to the Cyclone® V FPGAs community for the proper assistance. Regards, Leonardo C. Intel Customer Support Technician Under Contract to Intel Corporation
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