Warning: Can't generate programming files because you are currently using the Quartus II software in

[S_Dyn]

Hello.

I am currently using Quartus II ver 7 Web Edition.

May I know what does this error means?

Thank you.

S_Dyn

[sstrell]

Your title is cut off.  Can you provide more detail on what you are trying to do?  And why are you using an almost 20 year old version of Quartus?

[FvM]

Missing part of Warnung is "Evaluation Mode". Guess you managed somehow to enable Evaluation Mode in licensing dialog.

[S_Dyn]

Hi.

Could you explain more. I dont really understand what are you implying.

Thank you.

S_Dyn.

[S_Dyn]

Hi.

Below is the error

Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode.

I am try to load .sof file into the DE1 board. This board supports Cyclone 2. This is the only FGPA board available in my institution and I need to teach to my students in next 2 weeks.

After some googling, I notice the .sof file is not generated after compilation because  the software is in Evaluation Mode.

I need some suggestion to solve this.

[FvM]

Hi,
it should be possible to reset licensing mode of Quartus 7 Web Edition to free license, but I'm not sure how to. I remember that old Quartus Web Edition from time to time comes up with a message that license has expired. Refreshing the license isn't supported because the respective server doesn't exist since many years. One possible choice in the dialog is "Evaluation Mode" which must not be selected. I was always able to skip the dialog and operate the old software as before, but I don't know if there's an official solution.
The latest Web Edition supporting Cyclone and Cyclone II is 13.0.1, still available for download. In case of doubt, I'd try to install this version.

[S_Dyn]

Hi,

I did research to check weather cyclone II is supported by the latest Quartus version.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/devices-support.html#cyclone%C2%AEseries

Referring to the screen shot,  Quartus II 13.0.1 only start to support Cyclone III and above.

For Cyclone II, I need to install Quartus II 13.0sp1.  Do this version needs a paid license?

https://www.intel.com/content/www/us/en/software-kit/711920/intel-quartus-ii-subscription-edition-design-software-version-13-0sp1-for-windows.html

This QII  version also have 3 disk? Should I download all version?

Please kindly advice.

Thank you.

S_Dyn.

[FvM]

Hi,
you are confusing versions. 13.0.1 is 13.0sp1, you are showing device support info of 13.1

You minimally need two installation files from "Individual Files" tab, QuartusSetupWeb-13.0.1.232.exe 1.5 GB and cyclone_web-13.0.1.232.qdz, 569 MB.

Regards
Frank

[_AK6DN_]

As an FYI, I have a TerAsic DE1 board with the CycloneII device and I use Quartus Web 13.0sp1 to compile code for the board.

It works just fine. I have used it on XP and Win7 and now Win10; have not tried Win11.

So 13.0sp1 is the way to go forward.

[S_Dyn]

Hi.

Do this version need any license?

Thank you.

S_Dyn.

[_AK6DN_]

No, the web version of Quartus 13.0sp1 does not require a license. Just install and run. It supports the DE1 board directly.

[S_Dyn]

Hi.

I get the message when I open the QII.

Would I face the same issue where the .sof file is not generated after compilation because of the web version?

Thank you.

S_Dyn.

[_AK6DN_]

Select the second option "Run the Quartus II software" when you install.

You don't need or want the subscription version which requires a paid license, and
I am assuming you are not using any purchased IP files so the third option does not apply.

Once the web version is installed, it won't ask you again about licensing.

[S_Dyn]

Hi.

Thank you for the advise.

I have successfully install and run the software. 

Now I need to try to compile a Verilog code and load the code onto DE1 board.

S_Dyn

[S_Dyn]

Hi.

The loading of the program is failed

Please kindly assist.

Thank you.

S_Dyn.

[sstrell]

You set pins in the Location column, not the Fitter location column.  Fitter locations are locations assigned by the Fitter automatically during compilation.

[S_Dyn]

Hi.

Thank you for your help.

I have try your suggestion and it is successful.

But now I have issue in loading the .sof file.

This is the error.

Error (209015): Can't configure device. Expected JTAG ID code 0x020B60DD for device 1, but found JTAG ID code 0x020B30DD.

Any idea?

S_Dyn

[_AK6DN_]

Well, it depends on what TerASIC DEn board you are connected to.

I have both a DE2-70 with the EP2C70 (idcode 0x020B60DD) and a DE1 with the EP2C20 (idcode 0x020B30DD).

You said if found idcode 0x020B30DD which means you are connected to a board with an EP2C20 (or EP2C15, same code).

But you compiled for idcode 0x020B60DD which would be an EP2C70 device.

That is the problem. You need to specify the correct target device in Quartus prior to doing the compilation.

[S_Dyn]

Hi.

I have change the target device as per suggested.

Could you explain the reason behind this? What is the meaning of idcode? What is the different between the 2 devices. I assume that they are the same as they are in the same family.

Thank you.

S_Dyn.

[_AK6DN_]

Do you have the datasheet for the Cyclone II family devices? The JTAG ID codes and devices are described in great detail.

If you don't, download the "Cyclone II Device Handbook" from this page ...

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/cyclone-ii-support.html?s=AtoZ&f:@emtcontenttype_en=%5BDevelopment%20User%20Guides%5D

The IDcode is (usually) unique for each device in a family, and it lets the software tell what the device is via JTAG.

The EP2C20 and EP2C70 devices differ in the number of logic, memory, and I/O cells on the devices.

They have 20K and 70K logic cells respectively, as the device name indicates.

The basic architecture (ie, type of cell) is the same for each member of the family.

When you compile code in Quartus, you must target a particular device, eg, either EP2C20 or EP2C70 as the software
needs to know how big (number of logic cells) the device is and how they are laid out and connected. Code is compiled
and a .SOF file is generated for the specific device and they are not interchangeable.

[S_Dyn]

Hi.

I should have explore more. 

Thank you so much for the sharing.

S_Dyn.