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Honored Contributor I
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128 bit Avalon read/write

Hi, 

 

I am working on a class project that uses NIOS II to send 128 bit of data through Avalon bus to a custom logic to process and send back the data through Avalon to NIOS to display.  

 

I have an interface module between the avalon and my custom logic. I tried to use an index to point to which part of the 128 bit is to be chunk and put to the avalon bus each posedge clk, after that I use NIOS to produce multiple data and send to the bus but seem like this way doesnt work  

 

Anyone has an idea how to implement this ? 

 

Thanks
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Honored Contributor I
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The NIOS II processor only has a 32 bit interface. 

So, it will read/write data on 32 bit chunks. 

 

The NIOS II i also a master. You need to implement your custom logic as a proper Avalon-MM slave.
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Honored Contributor I
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Hi, let me clarify a bit of my problem 

 

In the interface module, I created an array of 128 bit and divided this into 4 range of 32 bit each. For every posedge clk signal, each 32 bit chunk will get an input. Something like this: 

//======================================== 

always@(posedge clk) 

if (index==0)begin fifo_in[31:0] <=wr_data; index=1;end //wr_data is to be //map with the write signal of avalon bus, which is the user input signal 

else if (index==1)begin fifo_in[63:32] <=wr_data; index=2;end 

else if (index==2)begin fifo_in[95:64] <=wr_data; index=3;end 

else if (index==3)begin fifo_in[127:96] <=wr_data; index=4;end 

 

On the other side, I wrote similar code for reading the result from the output of my custom logic, which is also 128 bit. 

 

My custom logic only need the chunk of data of128 bit to process and that is it, dont have to get another one. 

 

To run the test using NIOS, I create 4 32-bit data and use IOWR, then IORD to the base address 1 to get the result: 

 

a=0x00006464; 

b=0x00006464; 

c=0x00000000; 

d=0x00000000; 

 

IOWR(ADD_INTERFACE_0_BASE,1,a); 

IOWR(ADD_INTERFACE_0_BASE,1,b); 

IOWR(ADD_INTERFACE_0_BASE,1,c); 

IOWR(ADD_INTERFACE_0_BASE,1,d); 

 

j=IORD(ADD_INTERFACE_0_BASE,1); 

k=IORD(ADD_INTERFACE_0_BASE,1); 

l=IORD(ADD_INTERFACE_0_BASE,1); 

m=IORD(ADD_INTERFACE_0_BASE,1); 

 

It turn out that either write or read or both dont work. 

 

My question is: 

1. Is this problem come from the synchronize of the clk cycle between the custom logic and avalon bus (or something else) that the fifo_in never actually get enough chunk of data provided ? How to fix this ? 

2. On the read part, what is a good way to read from a 128 bit fifo_out through the avalon bus like above 

 

I have been with this in for a few days already and still get stuck. I would really aprreciate if anyone can help me out 

 

regards
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Honored Contributor I
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In the code snippet you posted, it does not appear your are checking for the Avalon "write" signal. Your code would attempt to store a word on each clock cycle even when there is no Avalon write taking place. 

 

Personally, I would probably use 2 address bits to split the 128 bit write into four separate 32 bit writes at consecutive word addresses. Then you don't need to keep track of an index manually as in the code you posted.
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Honored Contributor I
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Hi, 

 

I actually put this assignment in the code as well 

 

assign wr_en_add_1=cs & wr & addr; 

assign rd_en_add_1=cs & rd & addr; 

 

where cs,wr,rd,and addr are mapped to signal chipselect,write, read, and address of avalon in SOPC Builder. 

 

The write block above is actually like this 

 

always@(posedge clk) 

begin  

if (wr_en_add_1) 

begin 

if (index==0)begin fifo_in[31:0] <=wr_data; index=1;end //wr_data is to be //map with the write signal of avalon bus, which is the user input signal 

else if (index==1)begin fifo_in[63:32] <=wr_data; index=2;end 

else if (index==2)begin fifo_in[95:64] <=wr_data; index=3;end 

else if (index==3)begin fifo_in[127:96] <=wr_data; index=4;end 

end 

 

After I check with the above code, it seem like the avalon only take the first wr_data from NIOS, an ignore the rest when I want wr_data to have another value to assign to other fifo_in i.e my customer logic only receive fifo_in[31:0] ! 

 

Do you have any idea ? 

 

Thanks
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Honored Contributor I
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Have you tried changing the update of index to a non-blocking assignment? For example, do "index <= 1" instead of "index = 1".

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Honored Contributor I
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Hi, 

 

I have checked that also but still 

 

After lot of testing, i figure out that the LAST 32 bit value assigned by the software (i.e d=0x.....) is going to fulfill the whole 128 bit of my fifo_in !!! 

 

In this case, maybe this last value have overwritten the previous value to be the only wr_data data shown up to avalon 

 

Is there any other way to write ? What do you think? 

 

Thanks
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Honored Contributor I
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As I mentioned before, another way to do it would be to assign a different address to each 32 bit word. For example, you could do something like: 

always @(posedge clk) begin if(avs_s0_write) begin case(avs_s0_address) 2'd0: fifo_in <= avs_s0_writedata; 2'd1: fifo_in <= avs_s0_writedata; 2'd2: fifo_in <= avs_s0_writedata; 2'd3: fifo_in <= avs_s0_writedata; endcase end endThen, to write the 128 bits you would do something like: 

IOWR(ADD_INTERFACE_0_BASE,0,a); IOWR(ADD_INTERFACE_0_BASE,1,b); IOWR(ADD_INTERFACE_0_BASE,2,c); IOWR(ADD_INTERFACE_0_BASE,3,d);
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Honored Contributor I
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Hi, 

 

Is signal avs_s0_address mapped to any avalon signal ? Or I just simply declare it as a 2 bit reg ? 

 

Thanks
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Honored Contributor I
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It is the Avalon address signal.

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