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1098 Discussions

Building serial communication...

Altera_Forum
Honored Contributor II
1,673 Views

Hi, 

 

I am using a FLEX10K UP2 board and want to do some image processing on it. I would like to build an 8-bit internal RAM for my FPGA in order for my design file to write data to the RAM and read data from my CPU. I have been advised to use the serial communication to achieve data interaction between my CPU and FPGA. Since I am a beginner here, my questions would be: 

 

  • Any suggestion on creating internal RAM? By using and altsyncram and associate it to my design file? 

 

  • If so, then how to establish a serial commucation between my CPU and then internal RAM? Is SOPC Builder useful here? In the mean time, I have done some reading on UART, RS232, parallel-in-serial-out register and serial-in-parallel-out register. 

 

 

I really appreciate for any references related to above issues. 

 

Thanks.
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8 Replies
Altera_Forum
Honored Contributor II
328 Views

Due to the limited LE capacity of Flex10k, SOPC wouldn't be a good idea. 

 

Regarding simple UART reference designs. Did you notice the projects from opencores, e.g.: 

http://www.opencores.org/projects.cgi/web/uart/overview
Altera_Forum
Honored Contributor II
328 Views

Hi, 

If you don’t stick to serial communication, you can use In-System Sources and 

Probes to read and write a FPGA internal RAM.  

http://www.altera.com/literature/hb/qts/qts_qii53021.pdf 

 

This tool provides a kind of parallel I/O ports resident in your FPGA. You can control the I/O ports through a JTAG cable and a TCL script.
Altera_Forum
Honored Contributor II
328 Views

Basically a good suggestion, but not helpful wit Flex10k.

Altera_Forum
Honored Contributor II
328 Views

I don’t aware that the IP does not support Flex10k. Thanks for the correction.

Altera_Forum
Honored Contributor II
328 Views

I also nearly forgot, that there have been FPGA without SignalTap, Memory Content Editor and all these functions depending on virtual JTAG. I knew with Flex10k from a preceeding topic.

Altera_Forum
Honored Contributor II
328 Views

Hi, 

 

Thanks for all the advice. I now studying the design reference as provided in Opencores.org. 

 

But how do SignalTap, Memory Content Editor and all these functions affect my UART design? 

 

Thanks!!!
Altera_Forum
Honored Contributor II
328 Views

The said tools don't affect your design, cause they aren't available with Flex10K. Would be interesting tools otherwise.

Altera_Forum
Honored Contributor II
328 Views

If it helps I can send you my own UART IPcore. I wrote it for one of my projects. It requires 50 MHz clock signal and has user-set baudrate from 150 to 38400 bps. Write me an e-mail if you will need it (zaquadnik@gmail.com).

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