Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Can't get there from here

ABerg28
Beginner
376 Views

We use the Terasic DE-1 Boards for our Digital Electronics class. I would also like to use them for my Embedded Systems class. I would like to be able to do two things:

1- Have the students develop simple peripheral devices in the FPGA fabric, such as timers, buffers or I/O ports and connect them to the ARM core.

2- Bring the bus signals to the GPIO pins so the bus activity could be viewed with an external logic analyzer,

Surprisingly, there seems to be disagreement among faculty who teach in this area about whether or not it is possible to do this. My idea scenario is to create buffers that can sit on the address, data and status busses and output to the GPIO pins. Any help would be much appreciated.

Arnie

0 Kudos
5 Replies
AminT_Intel
Employee
344 Views

Hello Arnie, 

 

Both statements you mentioned above are possible. Here is the manual menu that you can refer to for this device: https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-4904342209-d...

 

Thanks

ABerg28
Beginner
341 Views

Hello AminT,

            I'm sorry if you didn't understand my post. I have the manual for the DE-1 board. We use them for our teaching. That isn't the issue at all. The issue is how to access the ARM bus inside the Cyclone V FPGA. After doing some research, I found a block diagram that shows why it probably isn't possible to do what I want to do. The reason is that there is a cache sitting between the ARM core and the FPGA fabric.

I can write to specific addresses and write through the cache, but that is only to specific addresses. I can't see the bus. Unless there is a way to turn off the cache and bring all bus signals through to the FPGA, I don't see how what I want to do would be possible.

Arnie

AminT_Intel
Employee
310 Views

Hello Arnie,

 

1. I think you are referring to the block ‘FPGA to HPS’ at the bottom of the figure Cyclone V SoC Hard Processor System on this page: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v/features.html. The logic implemented in FPGA part can be read by the ARM core through the “FPGA-to-HPS: Configurable 32, 64, or 128 bit AMBA AXI interface”. You would also want to monitor the AXI bus by using Signal Tap. 

2. You may have to duplicate the registers driving the AXI bus to the GPIO pins, so that they can be observed using external logic analyzer.

 

I hope this helps.

 

Thank you,

Amin

AminT_Intel
Employee
307 Views
AminT_Intel
Employee
272 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Reply