DE1-SoC: Problem with audio core for Altera DE-Series Boards in Avalon ST mode

[Altera_Forum]

I’m trying to use the University Program Audio core for the DE1-SoC Board with the Avalon streaming interface. 

 I used the IP cores for the audio config, pll and connect the audio signal source to the sink, so the design only loops the audio input from Line In to Line Out.   It somewhat works, but the problem is that I get a loud noise on the audio signal, I assume that the data format of the audio IP core doesn’t match with the format of the audio codec on the board.   It works without any noise when I directly connect audio_i2s_dacdat with audio_i2s_adcdat and audio_i2s_daclrck with audio_i2s_adclrck. Therefore, I suspect that there is an issue with the data format produced by the Audio IP core in the Avalon Streaming Mode.   Is there a working example, where the Audio Core is used in Streaming Mode without a Processor?   What Data Format should be used I2S or Left Justified?  qsys settings:   system clk 50 MHz audio pll 12.288 MHz   http://www.alteraforum.com/forum/attachment.php?attachmentid=13391&stc=1  http://www.alteraforum.com/forum/attachment.php?attachmentid=13392&stc=1  http://www.alteraforum.com/forum/attachment.php?attachmentid=13393&stc=1

[Altera_Forum]

I found the issue, i used the audio_pll (12.288MHz) for the audio ip core, now i'm using the 50MHz sys clk and it works. 

 But its strange that the design only works with 50MHz.

[Altera_Forum]

What do you use the Audio PLL for?

[Altera_Forum]

Are you sure the codec was actually function like you thought? I reproduced your work (Using the 50 Mhz clock) and used a logic analyzer directly against the pins of the Wolfsom chip, and found that there were no clock signals being produced, it seems that the codec went into line-in by pass mode. The only pins that were producing any sort of signal were the analog in and analog out pins.