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Honored Contributor I
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DE2-115 with HSMC_ADA from terasic

Hello, 

 

I was thinking about buying a DE2-115 and an HSMC_ADA from terasic. 

 

How do I know the DE2-115 can handle the amount of data coming in and out of the HSMC_ADA? 

 

How do I know what type of connection is between the FPGA and the ADA board. I can understand that it is HSMC but is it an LVDS signal? 

 

The DE2-115 has an EP4CE115 FPGA. The HSMC_ADA has two 14-bit ADCs and two 14-bit DACs running at 65 MSPS and 125 MSPS, respectively. 

 

Each ADC and DAC bit has their own pin.
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Honored Contributor I
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--- Quote Start ---  

 

I was thinking about buying a DE2-115 and an HSMC_ADA from terasic. 

 

How do I know the DE2-115 can handle the amount of data coming in and out of the HSMC_ADA? 

 

How do I know what type of connection is between the FPGA and the ADA board. I can understand that it is HSMC but is it an LVDS signal? 

 

The DE2-115 has an EP4CE115 FPGA. The HSMC_ADA has two 14-bit ADCs and two 14-bit DACs running at 65 MSPS and 125 MSPS, respectively. 

 

Each ADC and DAC bit has their own pin. 

--- Quote End ---  

All of this information should be in the resources provided by Terasic. 

 

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=67&no=278 

 

Why don't you read that information first, and then come back with specific questions. 

 

Cheers, 

Dave
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Honored Contributor I
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I did read user guide for the HSMC_ADA which is what confused me a lot. 

 

I read this document and the ADC spec sheet and I can't tell what type of interface between the DE2-115 and the HSMC_ADA other than the fact that it is HSMC. There are 14 output ports for the HSMC_ADA for each ADC and DAC inputs/outputs. So I assume that each port is running in parallel 1-bit at a time at 65 MHz for the ADCs and the DACs ports run in parallel 1 bit for each port at 125 MHz. 

 

However, what confuses me is that in the FPGA data sheet of the Cyclone IV, there are different types of I/Os that run at specific speeds of all which I have no idea how to interpret. All I know is I want to be able to receive 14-bits at 65 MHz which equals to 910 Mbps, and transmit at 1750 Mbps. How do I know what type of I/Os my board is going to be using so that I can understand based on the data sheet if the HSMC_ADA will receive/transmit @ full speed with my FPGA? 

 

PS Dave, I have seen an old post of yours where another student is inquiring about whether the DE2-115 trying to receive 14-bits at 65 MSPS via LVDS.  

 

.alteraforum.com/forum/showthread.php?t=28711 

 

Clearly he could not receive 14-bits @ 65 MSPS via LVDS, but my situation is different in the sense that I do not know if I am receiving in LVDS or not. This is what worries me because I don't exactly know how to interpret the FPGA IOs speeds and what type the HSMC_ADA uses (I am a student trying to learn these things). I'm trying to prevent myself from buying two boards that I have no idea if they will work in full capacity together.
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Honored Contributor I
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By the looks of the photos on the Terasic web site, and the fact that the board can connect via HSMC I/Os or via GPIOs, I'd guess that the signals are single-ended 3.3V or 2.5V LVCMOS.

 

The Terasic HSMC_ADC specification has some pinout details, but its not very explicit, so look at the schematic - I've attached it here.

 

The board uses 3.3V from the host board. The DE115 has jumpers for the HSMC power supply. You'll need to select 3.3V for the bank power.

 

The ADC/DAC use parallel buses at whatever speed you clock the ADC/DAC. The ADC and DAC each have a maximum frequency, but you can clock them at whatever frequency you like below that, eg. clock them both at 50MHz.

 

Cheers,

Dave

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