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MAX 10 LVDS serdes CDR

Altera_Forum
Honored Contributor II
2,007 Views

Hello, 

 

 

This is Doosoo Ha, senior engineer of Opticis.  

 

I am designing a LVDS serdes system using two(2) of MAX 10 devices.  

 

I plan to build LVDS serdes system as transmitting data with only one LVDS signal line.  

 

The LVDS using in my system is "LVDS with embedded clock". In other words, a separate clock signal for LVDS deserialization is not transmitted. I set LVDS serialize as factor is ‘10’ and the data rate as ‘100Mbps’.  

 

I confirmed LVDS output is normal when inputting K28.5 data to LVDS serialize block. 

 

After that, I designed deserialize block to LVDS deserialize block but problem has occurred during its verification. 

 

What it saying as a problem is that the clock was asynchronized during deserialization because it was designed with "without clock signal". 

I would like to know if there is any way clock not being asynchronized when I use LVDS with embedded clock without transmitting a separate clock signal for LVDS deserialization. 

 

Please assist me how I can solve this problem.
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4 Replies
Altera_Forum
Honored Contributor II
369 Views

As far as I know, there's no ready-made software CDR IP available for MAX10 and similar devices. It's however possible to perform receiver clock synchronization utilizing the PLL dynamic phase shift feature.

Altera_Forum
Honored Contributor II
369 Views

Thankyou. 

I will test it using the PLL dynamic shift feature.
Altera_Forum
Honored Contributor II
369 Views

hi 

I tried PLL Dynamic shift feature on there but PLL Dynamic shift feature didn't work. 

Can you provide me any example of PLL Dynamic shift code?
Altera_Forum
Honored Contributor II
369 Views

I can't disclose the design, only give a brief idea how it works. The data edges are compared with a shifted clock (180 degree in SDR design), depending on the comparison the PLL output phase is either shifted up or down.

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