Hello, I have a Terasic DE2-70 board and I am trying to run the demonstrator DE2_70TV.The .sof file that comes with the CD and the demonstrator downloaded internet is working perfectly, but if i recompile these projects and I put them again in the FPGA the image i get is noisy and with some vertical lines. :eek: My version of Quartus II 11.1 Web edition build 173. I would appreciate your help to solve this problem. Thank you! :D
i tried with Quartus 9.1 and with Quartus 10 both versions of the demonstrator. they work ok if you compile it with the corresponding version.But if i want to use the video decoding for another project, the same vertical lines appear. Do you know why? Thanks! Eze
Can you explain a little more about time constraints?And can you also explain how you have add the time constraints on the DE2-70TV I cant find the orginal time constraints.
there are in a file DE2_70_TV.sdcyou can add from settings, assignments • In Timing Analysis Settings, select Use TimeQuest Timing Analyzer during compilation. • In TimeQuest Timing Analyzer add the time constrains file. if then check the report of timing after compiling also if you have problem read a tutorial about TimeQuest, it is short :)