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1082 Discussions

DE2-70 - DE2_70TV demonstrator is not working

Altera_Forum
Honored Contributor II
1,364 Views

Hello, I have a Terasic DE2-70 board and I am trying to run the demonstrator DE2_70TV. 

 

The .sof file that comes with the CD and the demonstrator downloaded internet is working perfectly, but if i recompile these projects and I put them again in the FPGA the image i get is noisy and with some vertical lines. :eek: 

 

My version of Quartus II 11.1 Web edition build 173.  

 

I would appreciate your help to solve this problem. 

 

Thank you! :D
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6 Replies
Altera_Forum
Honored Contributor II
83 Views

i tried with Quartus 9.1 and with Quartus 10 both versions of the demonstrator. they work ok if you compile it with the corresponding version. 

 

But if i want to use the video decoding for another project, the same vertical lines appear. Do you know why? 

 

Thanks! 

 

Eze
Altera_Forum
Honored Contributor II
83 Views

Hey eze1785, 

 

I have the same problem as you have. 

Do you have any solution for this problem in the meantime
Altera_Forum
Honored Contributor II
83 Views

you have to add the time constraints that come with the original program

Altera_Forum
Honored Contributor II
83 Views

Can you explain a little more about time constraints? 

 

And can you also explain how you have add the time constraints on the DE2-70TV I cant find the orginal time constraints.
Altera_Forum
Honored Contributor II
83 Views

there are in a file DE2_70_TV.sdc 

you can add from settings, assignments 

• In Timing Analysis Settings, select Use TimeQuest Timing Analyzer during compilation.  

• In TimeQuest Timing Analyzer add the time constrains file.  

 

if then check the report of timing after compiling  

 

also if you have problem read a tutorial about TimeQuest, it is short :)
Altera_Forum
Honored Contributor II
83 Views

I dont have the DE2_70_TV.sdc file in the Demonstrations/DE2-70_TV map 

Must I create it first or is this a fault on the cd.
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