I have installed UP IP's from Altera and set the path to them in SOPC Builder. I have found that the component names for DE2_Basic_Computer example were incorrect for the Quartus II 8.1 setup. I have corrected them (from altera_up_avalon_parallel_port_classic to altera_up_avalon_parallel_port and so on). However, there are now inconsistencies on port names in the VHDL nios_system component. So, it seems clear that this example was prepared for an older Quartus II/SOPC Builder version.Has somebody modified it to run on Quartus II 8.0 or newer versions? If so, may be he/she could share the code in this forum. That would be greatly appreciated.
Hi,I've got the same problem, except I am using a DE2-70 board. To fix the problem with the wrong modules, I removed all the non-existent ones, and re-added the newer (9.0) ones, ensuring that the base addresses, IRQ and settings matched the original one. I was then able to generate the new system. However if you have a DE2-70 board, you run into a ton of trouble since the Verilog for the Basic Computer assumes you have a DE2 board, and so you have to spend a bit of time trying to re-organise all the missing inputs/outputs for the SSRAM chip of the DE2-70. I managed to get it to build, but my biggest query is that there is no CLK for the SSRAM/SRAM!? Am I confused here, but I see no way for the SRAM to be clocked. Did you notice this?? Ross..