DE2 Board, design loads but doesn't run

[Altera_Forum]

Hey 

 Currently trying to get my traffic lights system to run on the Altera DE2 board. Its simulated and all working in the software however when i program it to the board it shows the initial state in the LED's but doesn't run. It doesn't respond to any change in inputs either.  Has anyone else came across this? Im still new to all this so any advice would be very helpful! Thanks

[Altera_Forum]

Can you post your code so qe can take a look and may spot a problem? 

I assume your pinout and pin assignmennts are correct, do you havethe same problems with other designs?

[Altera_Forum]

Yeah, im having this problem with numerous designs. 

  Library ieee; Use ieee.std_logic_1164.all;  Entity trafficlights is  Port (SenA, SenB, Clk, Init: in bit;  Lights: out bit_vector (5 downto 0)); End trafficlights;  Architecture moore of trafficlights is  Type state_type is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11);  Signal state: state_type;   Begin  Process (Clk, Init)  begin  if Init ='1' then state <= S0;  elsif Clk= '1' and clk'event then  case state is  when S0=> if SenA ='0' and SenB ='0' then state<=S1;  elsif SenA ='0' and SenB ='1' then state<=S4;  elsif SenA ='1' and SenB ='0' then state<=S0;  elsif SenA ='1' and SenB ='1' then state<=S1;  end if;  when S1=> if SenA ='0' and SenB ='0' then state<=S2;  elsif SenA ='0' and SenB ='1' then state<=S2;  elsif SenA ='1' and SenB ='0' then state<=S2;  elsif SenA ='1' and SenB ='1' then state<=S2;  end if;  when S2=> if SenA ='0' and SenB ='0' then state<=S3;  elsif SenA ='0' and SenB ='1' then state<=S3;  elsif SenA ='1' and SenB ='0' then state<=S3;  elsif SenA ='1' and SenB ='1' then state<=S3;  end if;   when S3=> if SenA ='0' and SenB ='0' then state<=S4;  elsif SenA ='0' and SenB ='1' then state<=S4;  elsif SenA ='1' and SenB ='0' then state<=S4;  elsif SenA ='1' and SenB ='1' then state<=S4;  end if;  when S4=> if SenA ='0' and SenB ='0' then state<=S5;  elsif SenA ='0' and SenB ='1' then state<=S5;  elsif SenA ='1' and SenB ='0' then state<=S5;  elsif SenA ='1' and SenB ='1' then state<=S5;  end if;  when S5=> if SenA ='0' and SenB ='0' then state<=S6;  elsif SenA ='0' and SenB ='1' then state<=S6;  elsif SenA ='1' and SenB ='0' then state<=S6;  elsif SenA ='1' and SenB ='1' then state<=S6;  end if;  when S6=> if SenA ='0' and SenB ='0' then state<=S7;  elsif SenA ='0' and SenB ='1' then state<=S6;  elsif SenA ='1' and SenB ='0' then state<=S10;  elsif SenA ='1' and SenB ='1' then state<=S7;  end if;  when S7=> if SenA ='0' and SenB ='0' then state<=S8;  elsif SenA ='0' and SenB ='1' then state<=S8;  elsif SenA ='1' and SenB ='0' then state<=S8;  elsif SenA ='1' and SenB ='1' then state<=S8;  end if;  when S8=> if SenA ='0' and SenB ='0' then state<=S9;  elsif SenA ='0' and SenB ='1' then state<=S9;  elsif SenA ='1' and SenB ='0' then state<=S9;  elsif SenA ='1' and SenB ='1' then state<=S9;  end if;  when S9=> if SenA ='0' and SenB ='0' then state<=S10;  elsif SenA ='0' and SenB ='1' then state<=S10;  elsif SenA ='1' and SenB ='0' then state<=S10;  elsif SenA ='1' and SenB ='1' then state<=S10;  end if;  when S10=> if SenA ='0' and SenB ='0' then state<=S11;  elsif SenA ='0' and SenB ='1' then state<=S11;  elsif SenA ='1' and SenB ='0' then state<=S11;  elsif SenA ='1' and SenB ='1' then state<=S11;  end if;  when S11=> if SenA ='0' and SenB ='0' then state<=S0;  elsif SenA ='0' and SenB ='1' then state<=S0;  elsif SenA ='1' and SenB ='0' then state<=S0;  elsif SenA ='1' and SenB ='1' then state<=S0;  end if;  end case;  end if;  end process;    Process (state)  Begin  Case state is  When S0 => (Lights) <= "001100";   When S1 => (Lights) <= "001100";  When S2 => (Lights) <= "001100";  When S3 => (Lights) <= "001100";  When S4 => (Lights) <= "001100";  When S5 => (Lights) <= "010100";  When S6 => (Lights) <= "100001";  When S7 => (Lights) <= "100001";  When S8 => (Lights) <= "100001";  When S9 => (Lights) <= "100001";  When S10 => (Lights) <= "100001";  When S11 => (Lights) <= "100010";  end case;  end process; end Moore;

[Altera_Forum]

for the next time use code tags.  

At first glance I don't see anything wrong, are your pin assignments correct?

[Altera_Forum]

My understanding on ctags is still pretty lacking, but its something i definitely need to use more. 

 As for pins, ive check them all. They're all correct and each component is working.

[Altera_Forum]

with the code tags I meant tags you give in your post that makes the code appear in monospace font. 

What you could do to debug is using the lights to give the state indication. Now some have the same lights, if you change that you know for sure it waits in s0 and not in e.g. s4.

[Altera_Forum]

What drives your Init input? Is your logic being held in reset? Either that or you're not getting a clock. Not much else it could be.