DE2 Lab 7, Part 7 (VHDL) - Digital Logic

Altera_Forum · ‎08-25-2010

I just started learning VHDL and FPGA programing a couple of weeks ago and am currently working on Lab 7, Part 7 of the DE2 digital logic VHDL labs provided by Altera.

In this lab you have to code two finite-state machines. One for a scrolling 'hello' and another to determine what speed it should scroll at, judging on the key button the user presses.

I'm having trouble with the FSM that recognizes the speed. As it explains in the lab, if you press KEY(1) it increases in speed and if you press KEY(2) it decreases. I want to make this on the falling edge of each key press so that there is only one state change for each button press.

Here is the code I have for the FSM. Obviously this isn't correct and won't compile but I'm just copying it to illustrate where I'm stuck:

   PROCESS (KEY(1), KEY(2))
   BEGIN 
      CASE y2 IS
         WHEN A =>
            IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN 
               y2 <= B;
            ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN 
               y2 <= D;
            END IF;
            Stop <= 50000000;
         WHEN B =>          
            IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN 
               y2 <= C;
            ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN 
               y2 <= A;
            END IF;
            Stop <= 25000000;
         WHEN C =>
            IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN 
               y2 <= C;
            ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN 
               y2 <= B;
            END IF;
            Stop <= 12500000;
         WHEN D =>
            IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN 
               y2 <= A;
            ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN 
               y2 <= E;
            END IF;
            Stop <= 100000000;
         WHEN E =>
            IF ((KEY(1)'event) AND (KEY(1) = '0')) THEN 
               y2 <= D;
            ELSIF ((KEY(2)'event) AND (KEY(2) = '0')) THEN 
               y2 <= E;
            END IF;
            Stop <= 200000000;                       
      END CASE;      
   END PROCESS;

For clarification, the variable 'Stop' tells my other FSM how many clock cycles it should go through before moving the letters left.

Clearly the FSM has trouble with the two clocks (the key presses) for every state. What approach could I take to solve this problem? My previous FSM is clocked by a single clock but here I have to worry about two and the states depend on which one is pressed so I'm a little stuck with ideas.

Just to point out, I could just use KEY(1) = '0' instead of making it depend on the falling edge but in that case it would immediately jump to the last state and I only want 1 state to change with 1 button press. Hopefully this all makes some sense :)

Altera_Forum · ‎08-25-2010

Dont use the keys as clocks.

You're asking for trouble.

Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do:

if key(0) = '0' and key_old(0) = '1' then

Clocking the process will also get you away from the incomplete sensitivity list you have at the moment.

Altera_Forum · ‎08-26-2010

--- Quote Start ---

Dont use the keys as clocks.

You're asking for trouble.

Clock the process with the system clock. You can make a falling edge detector by registering the key states, then you can do:

if key(0) = '0' and key_old(0) = '1' then

Clocking the process will also get you away from the incomplete sensitivity list you have at the moment.

--- Quote End ---

Thanks a lot for the advice, exactly what I was looking for. I implemented your method and it works great. Thanks.