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Altera_Forum
Honored Contributor I
1,444 Views

DE2 Laboratory 8 bit wide mux (VHDL)

Hi guys, 

After 10 years of leaving high school, and 5 years after purchasing a DE2 board, I found time again to start playing with FPGA’s. 

So I started where everybody does (I think), with the lab exercises. And I’m already struggling with the 2[SUP]nd[/SUP] part of the 1[SUP]st[/SUP] lab. 

The exercise is to make an 8 bit wide, 2-to-1 mux. 

My code is: 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

 

ENTITY entitypart2 IS 

PORT( x : IN std_logic_vector (7 DOWNTO 0); 

y : IN std_logic_vector (7 DOWNTO 0); 

s : IN std_logic; 

M : OUT std_logic_vector (7 DOWNTO 0); 

ledupper : OUT std_logic_vector (7 DOWNTO 0); 

ledlower : OUT std_logic_vector (7 DOWNTO 0)); 

END entitypart2; 

 

ARCHITECTURE mux OF entitypart2 IS 

BEGIN 

ledupper <= y; 

ledlower <= x; 

M <= x WHEN (s = '0') ELSE y; 

END mux; 

 

X and y are routed to switches 0 to 7 and 8 to 15, M is routed to the green LED’s. The “ledupper” and “ledlower” are just added to see if something happens when I switch. 

 

The problem is: nothing happens!! If you don´t count that only LEDG7 goes on when I switch SW4 and all the red LED’s are on. 

What is wrong? In the RTL viewer, I see a (one) nice 2-to1 mux with x and y as input bus and M as output bus. 

Do I have to see 8 different mux’es?
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2 Replies
Altera_Forum
Honored Contributor I
218 Views

Do u assign pins with the pin planner? In the RTL viewer u'll see on mux, but the inputs and outputs will be 8 bit vectors. Do u see that? Or the inputs are 1 bit long?

Altera_Forum
Honored Contributor I
218 Views

I loaded the pin file from the file from the website and assigned the pins in the schematic topfile. 

And I see 8bit vectors in the RTL viewer. Exercise 3 is working without problems.
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