De2-115 remove the default project

[mitsvoid]

Hi everyone,

I hope you are all doing well. I am a bit confused about the default configuration on the board. I am trying to create an audio project or any other project, and I realized that, if I plug in a microphone or my phone into the line-in and speakers, the board will play sound. What I want to ask is, how can I remove this default configuration? I thought that if I compile a new project and upload it to the device, the previous configuration would be removed.

I hope I have made myself clear in my question, I would greatly appreciate your advice

Thank you.

[_AK6DN_]

You are probably compiling your project into a .sof file and downloading it directly into the FPGA configuration RAM.

It will be active UNTIL you power cycle the board as the RAM configuration does not persist without power.

At power up the configuration EPROM will be read and loaded into the device (the boards are normally setup to do this).

So that is why if you power cycle the board the 'default' configuration stored in the config EPROM reappears.

What you need to do, besides compiling your project to a .sof file, is use the Quartus tool quartus_cpf to generate a config EPROM .jic

which you can then download to the EPROM.

For example I run:

quartus_cpf -c DESIGN.cof

where DESIGN.cof contains:

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
	<eprom_name>EPCS64</eprom_name>
	<flash_loader_device>EP4CE115</flash_loader_device>
	<output_filename>DESIGN.jic</output_filename>
	<n_pages>1</n_pages>
	<width>1</width>
	<mode>7</mode>
	<sof_data>
		<user_name>Page_0</user_name>
		<page_flags>1</page_flags>
		<bit0>
			<sof_filename>DESIGN.sof</sof_filename>
		</bit0>
	</sof_data>
	<version>4</version>
	<options>
		<map_file>1</map_file>
	</options>
</cof>

And you will want to add the Altera serial flash loader module into your top level module as well (assuming verilog here):

    // Altera Serial Flash Loader module

    // Allows external JTAG access to the serial config eeprom for programming

    sfl	sfl
	( .asdo_in		(1'b0),		// not used
	  .dclk_in		(1'b0),		// not used
	  .ncso_in		(1'b0),		// not used
	  .noe_in		(1'b0),		// always enabled
	  .asmi_access_granted	(1'b1),		// external JTAG access always
	  .asmi_access_request	(),		// not used
	  .data0_out		()		// not used
	  );

[mitsvoid]

Hi, Thank you for the prompt reply. I will check it and will update.

[_AK6DN_]

You ought to view this ...

https://www.intel.com/content/www/us/en/docs/programmable/683299/current/using-the-fpga-serial-flash-loader-ip-85096.html

[mitsvoid]

Hi, after some search, I created the .jic file. However, in my programmer, when I started the progress, it failed. I think that it is  downloading to the board because the LCD is removed ("welcome to the Altera DE2-115" is displayed), and the LEDs are off. Surprisingly, even now, if I plug in a speaker with a mic, the board plays sound.

Please find the attached photos. What am I missing?Also if i select file type .jic the only choice for configuration device is EPCQL1024.

Is it not possible to completely remove the default project when I power up the device?

[_AK6DN_]

How are you setting the RUN/PROG switch on the DE2-115 board? Per the user manual:

1. RUN - JTAG mode - select a .sof file and write it directly to the FPGA
2. PROG - AS active serial mode - select a .pof file and write it to the EPCS configuration device

Normally I keep my boards in JTAG (ie, RUN) mode and embed the IP module alt_serial_flash_loader module
into my design so that the EPCS configuration device is made to show up in the JTAG chain as a second
device. Then I can use the .jic file to program that device. It does require that the FPGA have code running
in it with an active SFL module, otherwise it won't appear, and you have to use mode (2) above.

[mitsvoid]

Hi, I just ran "RUN - JTAG mode - select a .sof file and write it directly to the FPGA" .

Surprisingly, even without any pin planner assignment or other configurations, the board plays sound when I connect a speaker and microphone. Additionally, when I compile the project and download it to the device, the LCD displays 'Welcome to the Altera DE2-115.' Is this normal?

Also, please find the steps that i have follow to create a .jic file and add a flash drive to my project?

1. From 'Files,' convert programming files, and create the .jic file (adding the board and .sof file).
2. In the programmer, go to 'Edit' -> 'Attach Flash Device.' Quartus allowed me to choose only the EPCQL1024 with the .jic file, but the process failed."

Thank you.

[_AK6DN_ · Accepted solution]

The DE2-115 is a pretty old board, around since 2012; I got mine back in 2015 and it uses an EPCS64 device for program storage.

I use QuartusII 16.0 for development it it works exactly as the documentation specifies.

When did you get your board, and what version of Quartus are you using?

Are you aware of: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=502#contents

[mitsvoid]

The board was provided to me by the university and it was new.
Quartus version is 22.1 .Yes, I know that but is something that i missing on link you provided me?
Please can you let me know if this is normal when I compile the project and download it to the device, the LCD display shows "Welcome to the Altera DE2-115" even without any pin programmer assignment or other configurations?

[_AK6DN_]

If you look here:

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=4#contents

The link to the user manual is available as a PDF file.

On pages 12-13 section 2.3 it describes the behavior of the default program in EPROM provided on a new board.

The welcome message you indicate is written to the LCD. And the sound behavior you described is present.

So if you continue to see that message you are not overwriting the default program in EPROM.

I would suggest that you download the support CDROM from the TerAsic site and follow their examples.

[NazrulNaim_Intel]

Hello,

I’m glad that your question has been addressed, for now I will set this case to Close-Pending. 

Regards,

Nazrul Naim