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Altera_Forum
Honored Contributor I
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External bus Bridge

Hello everyone,  

I would like to know how to stop/disable the Avalon to external Bus bridge time out control signal?  

I want NIOS processor to wait till it receives an acknowledge signal from the external device.  

Please suggest.
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Altera_Forum
Honored Contributor I
21 Views

 

--- Quote Start ---  

 

I would like to know how to stop/disable the Avalon to external Bus bridge time out control signal?  

I want NIOS processor to wait till it receives an acknowledge signal from the external device.  

 

--- Quote End ---  

 

 

The waitrequest signal is used to stall a master on the Avalon bus. 

 

In your case, your NIOS processor would start a read or write transaction, and if it finds the waitrequest signal high, it will stall until that signal goes low. This allows the controller for your external logic to implement the read or write transaction. Typically for a write, your FPGA logic would accept the data, and deassert the waitrequest signal to allow the processor to proceed, and then your controller would write to the external device (this is a posted write). If the NIOS processor tries writing or reading while the external device controller is busy, it would see waitrequest high, and be stalled until your controller is ready. 

 

If your external device is really slow, eg., an SPI device or I2C EEPROM, then rather than stall the NIOS II processor while the serial transaction completes, you should create a controller with a control registers interface, eg., a data output/input register, and an interrupt or status bit to indicate when the controller is done. 

 

Cheers, 

Dave