Hi, I am working on implementing the FFT megacore in my project and I am seeing a couple problems. Here is the info on my FFT:Variable Streaming Architecture Fixed Point Natural Order for both Input and Output Quad Output Engine Transform Length of 4096 Data Precision of 12 bits Twiddle Precision of 12 bits Targeting the Cyclone II Here are my questions/issues: 1) I send the FFT the SOP signal and then 4096 clock cycles later (4096 because that is my transform length) I send it the EOP signal. Randomly I am getting all the error messages (01 - Missing SOP, 10 - Missing EOP, and 11 - Unexpected EOP). So my question is, what am I doing wrong? Does the clock sample at rising edge or falling edge? Is the SOP and EOP valid on the rising edge or falling edge? Am I correct in separating the SOP and EOP by 4096 clock cycles? 2) I have a data precision of 12 bits so I input 12 bits real and 12 bits imaginary. On the output I get 27 bits real and 27 bits imaginary. I believe that I get so many bits because of the scaling factor, is that correct? How can I determine which bits of those are the valid bits? Thank you for any insight you can provide!
are you taking a look at the sink_ready output signal of the FFT core? you'll need to take a look at the FFT User Guide and the Avalon Interface Specifications to make sure you have the Avalon Streaming protocol correct
All is sampled on rising edge.Your SOP shall be your first DATA input, your EOP shall be your last DATA So you'll have 1) SOP & VALID & D0 2) DVALID & D1 till D4094 3) EOP & D4095 Hope is clear enough Best regards
Thanks for the help on the SOP/EOP timing. I think I got all that figured out but I am still lost on how to scale my output to get the correct 12 bits. Does anyone have insight on how to do this?Thanks!