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Altera_Forum
Honored Contributor I
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FPGA to HPS Communication

Hi Friends, 

I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and store it in the SDcard. So the idea is to develop a small program in the Linux which listens to some port (internal) from FPGA and writes the data to a text file as soon as it get a new data. 

As I researched over the Internet , I came to know that I can use the AXI bus from FPGA to HPS and transfer as a burst data. The problem is I could not find a proper document , how to do it. 

Does anyone have an idea how to do this ? Any help would be greatly appreciated. 

 

Best Regards.
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8 Replies
Altera_Forum
Honored Contributor I
163 Views

Hi, 

 

You coud focus on an DMA and write your data directly through the SDRAM-Ports of the FPGA. After finishing one data-frame your core should send an Interrupt to the processor. 

 

You may want to read [1] from page 215. 

 

[1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf
Altera_Forum
Honored Contributor I
163 Views

Hi , 

Thanks for the answer :) 

Should I use the Nios ii for this ? . My design actually scans some GPIO ports from the board and I have convert it into a file. For this I have to transfer these data chunks to the RAM and access from Linux. So I have already a small VHDL module scans the ports and put these data into a FIFO. Now I have use DMA to transfer the data to RAM. 

Is it possible to use without Nios ii ? I mean with the DMA ip , is it possible to write a small VHDL module and send data to the memory via this IP through DMA? 

Do you have a link /tutorial with minimal example with DMA , both hardware and software ? Its ok if it is with Nios ii 

 

Best Regards.
Altera_Forum
Honored Contributor I
163 Views

Hi, 

 

you could try to use google. Try "nios dma" or "hps dma". We are not here to do your google search. If you have concrete questions do not hesitate to ask. 

 

And: Of course it is possible to control the DMA with a VHDL-module. But at first read the documentation provided.
Altera_Forum
Honored Contributor I
163 Views

Hi Tazz1984, 

 

Thanks for your reply. I have read the document. Unfortunately the document stresses more on Nios II processor, in my case in not much useful. I have some huge chunks of data and using Nios will again slow down my system. Its hard to find any example with HPS DMA as you suggested. I understand the theory behind it, but I am new in hardware design. How can I use the generated VHDL module and send these DMA signals. For eg, I have instantiated ( attached screeshot ) the DM controlled via Qsys and connected it to the HPS_SDRAM via Avalon interface. Now how will I use it ? through which inputs I should send the DMA commands and data ? . I tried in google all, but unfortnaltey could not find an answer. 

 

The following are the generated interfaces. 

component FPGA2SDRAMSCDMA is port ( clk_clk : in std_logic := 'X'; -- clk memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba memory_mem_ck : out std_logic; -- mem_ck memory_mem_ck_n : out std_logic; -- mem_ck_n memory_mem_cke : out std_logic; -- mem_cke memory_mem_cs_n : out std_logic; -- mem_cs_n memory_mem_ras_n : out std_logic; -- mem_ras_n memory_mem_cas_n : out std_logic; -- mem_cas_n memory_mem_we_n : out std_logic; -- mem_we_n memory_mem_reset_n : out std_logic; -- mem_reset_n memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n memory_mem_odt : out std_logic; -- mem_odt memory_mem_dm : out std_logic; -- mem_dm memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin sgdma_0_csr_irq_irq : out std_logic -- irq ); end component FPGA2SDRAMSCDMA; u0 : component FPGA2SDRAMSCDMA port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin sgdma_0_csr_irq_irq => CONNECTED_TO_sgdma_0_csr_irq_irq -- sgdma_0_csr_irq.irq );  

 

Thanks in advance
Altera_Forum
Honored Contributor I
163 Views

Added a clear screen shot-

Altera_Forum
Honored Contributor I
163 Views

The relavant interface is the csr-Interface, from which you may control the DMA. 

 

You may connect it directly to the LWHPS2FPGA-Port of the HPS. (Needs to be configured in the HPS [Lightweight-Bridge]) and use dedicated SW for that. Afterwards you may use VHDL instead of a SW-Description.
Altera_Forum
Honored Contributor I
163 Views

Hi, 

What do you mean my dedicated Software ? . Will the HPS [Lightweight-Bridge]) will slow down ? I need to transfer huge amount of data . 

Do you have some example somewhere ? Altera manual doesn't give anything about this. 

 

Best Regards.
Altera_Forum
Honored Contributor I
163 Views

Hi, not sure if it is still relevant at this point of time, but here are examples where data are moved from the HPS domain to the FPGA domain and vice versa. 

https://rocketboards.org/foswiki/view/projects/datamover 

https://rocketboards.org/foswiki/view/projects/cyclevsocsdramperformanceexampledesign
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