Finite state machine problem

[Altera_Forum]

Hi,  

 I have a state machine with 32 states. Assume the states transitions are sequential following the state number (ie it start at state 32 and followed by state 1 and followed by state 2 ..). I can go through state 32 to 24 perfectly. But after state 24 the fsm go to the reset state which is state 32. This is an incorrect behaviour. The FSM should transit to state 25. The transition logic for state 24 to state 25 is correct and i have tested with state 24 as reset state.   The board i am working on is UP1 board ( FLEX10K50R ). Any help is appreciated.   Many thanks,   noeman

[Altera_Forum]

Is the project schematic capture or HDL VHDL Verilog?

[Altera_Forum]

I made the project in VHDL files only. Also the state machine diagram given in the compliation summary is correct like i designed, but still it behave incorrect like i mention in the first post. 

 EDIT I am using Quartus II 8.1 Web Edition.

[Altera_Forum]

Simply assume a non-obvious design error.

[Altera_Forum]

If i remove all logic around the fsm, then it runs correctly.