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Altera_Forum

Honored Contributor I

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02-01-2009
11:21 PM

2,141 Views

Generate Triangular Wave Table

Hello!

I'm doing a project at school using the DE2 board as the digital controller of a DC-AC inverter. The goal is to output a 120V 60Hz sine wave from a ~300VDC input. Right now the design uses a ADC to read in the values of current output (scaled down of course) and this is to be compared with the Altera board to a 60Hz triangular wave (of equal magnitude scale) so that the board can control the gates of the inverter. I read this post on the forum: http://www.alteraforum.com/forum/showthread.php?t=4365&highlight=triangle but I'm still a little confused. One person suggested doing the triangle wave in logic (accumulator) and other people mentioned the Altera Megafunction generator. My plan was to either save in the values of the perfect 60Hz triangular wave to a table that can be compared to the value read in from the ADC and control the correction accordingly. I read on another post about using Matlab to generate VHDL code? Is it possible to make a triangle function in Matlab then export it some how to VHDL? Thanks a bunch guys, -JLink Copied

7 Replies

Altera_Forum

Honored Contributor I

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02-02-2009
09:38 AM

280 Views

Hi,

Things are done in different ways. For a triangular wave I will use a counter. It is easy but there are some subtleties. Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from (-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement) The following untested code gives you the idea of getting 100 samples per period: The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples) signal count : signed(7 downto 0); ------ process(reset,clk) -- assuming clk = 6KHz if reset= '1' then count <= -125; updown <= '0'; elsif rising_edge(clk) then if updown = '0' then if count < 125 count <= count + 5; end if; if count = 120 then updown <= '1'; end if; else -- if updown = '1' then if count >-125 count <= count - 5; end if; if count = -120 then updown <= '0'; end if; end if; end if; end process; output <= std_logic_vector(count);
Altera_Forum

Honored Contributor I

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04-26-2010
01:24 PM

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Altera_Forum

Honored Contributor I

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04-27-2010
07:12 AM

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Declare count as:

signal count: signed(7 downto 0);
Altera_Forum

Honored Contributor I

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04-29-2010
02:04 PM

280 Views

Altera_Forum

Honored Contributor I

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04-29-2010
02:07 PM

280 Views

Altera_Forum

Honored Contributor I

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04-29-2010
02:46 PM

280 Views

Don't read too much into my syntax and especially >, < etc.

The purpose is to give the idea only. A neat way is to have two states (s1,s2) in s1 : count goes up and change state in s2: count goes down and change state
Altera_Forum

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06-16-2010
12:20 PM

280 Views

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