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HPS FPGA UARTs Mapping Change

EFroh
Beginner
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Hi,

The HPS FPGA UARTs are automatic mapped in the 'build tree'- one to Linux kernel, and other to u-boot.

How do I map one UART to both?

 

Thanks.

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Fawaz_Al-Jubori
Employee
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Hello,

Can you elaborate more about your question?

Is this the HPS UART? Are you going to use this UART for serial terminal or data communication?

 

Thank you

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EFroh
Beginner
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Hi,

There is one UART that works right on the board.

I have an Arria 10 HPS processor that communicates with different peripherals..

I want to use this UART for the u-boot and the Linux both, for CPU stdio interface (serial terminal communication).

But the UART 0 is mapped to the Linux and UART 1 is mapped to the u-boot.

I tried to enable 2 or 1 UARTs on the Pin MUX peripherals GUI , but that didn't solve the problem, 

when I enabled one UART, the u-boot UART is disabled from the build tree mapping. and only Linux UART is works

 

Can you please help me with it?

Thanks.

 

 

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EFroh
Beginner
1,232 Views

I attached a snapshot.

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Fawaz_Al-Jubori
Employee
1,232 Views

I presume you are using the A10 SDMMC boot, with GHRD design. In GHRD design, UART is configured with dedicated IO. You can ensure same UART node configuration in both U-Boot device tree and Linux device tree., and serial0 is specified.

 

Example UART node configuration at U-Boot DTS

    

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10_socdk.dtsi

aliases {

       ethernet0 = &gmac0;

       serial0 = &uart1;

       i2c0 = &i2c1;

    };

 

 

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10_socdk.dtsi

&uart1 {

    u-boot,dm-pre-reloc;

    status = "okay";

};

 

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10.dtsi

uart0: serial0@ffc02000 {

           compatible = "snps,dw-apb-uart";

           reg = <0xffc02000 0x100>;

           interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;

           reg-shift = <2>;

           reg-io-width = <4>;

           clocks = <&l4_sp_clk>;

           resets = <&rst UART0_RESET>;

           status = "disabled";

       };

       uart1: serial1@ffc02100 {

           compatible = "snps,dw-apb-uart";

           reg = <0xffc02100 0x100>;

           interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;

           reg-shift = <2>;

           reg-io-width = <4>;

           clocks = <&l4_sp_clk>;

           resets = <&rst UART1_RESET>;

           status = "disabled";

       };

 

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