Hi, first time posting. I am new to Q II and FPGAs and am trying hard to learn but am handicapped in that I have very little VHDL experience and no courses under my belt, just self instruction (and I'm not a spring chicken(:>)).I have created a simple state-machine using the wizard. I then generated the VHDL file. I don't think it matters but I modified the VHDL state-machine to display the state variables since the wizard doesn't seem to allow this. So lets just say I have created a VHDL state-machine having Moore outputs and a number of inputs that will ultimately come from a bdf schematic but initially are just pins of the DE-2 kit. This VHDL SM works, it seems. Seems, because I have issues with the active level of the signals, i.e. the DE-2 pushbuttons sit high and I want the opposite, etc. I really don't want to have to commit to a particular active level if possible since this should be something that can be easily altered at any time. I would normally address this via port properties in a bdf but can't seem to do this via the state-machine format?? That's one issue. However I would like to utilize the SM in a more extensive bdf file that would generate some of the inputs that are used by the SM. Having never done this I am running into problems. There are clashes over entities and libraries - I don't have the exact messages to refer to at this moment. Any advice regarding combining files in a single project such as I wish to do would be much appreciated. Jack
You can use the "create HDL from current file" in order to obtain a VHDL or Verilog file that can be added to your project and instantiated in the top level entity.Otherwise, if you prefer schematic, you can "create symbol" from current file. This creates a symbol that you can instantiate in a top level bdf file. I've no clue on how to handle the active low/high levels of the pushbuttons in the automatically created state machine.
Thanks, your reply gives me information as to the general nature of the challenge. However, I am very handicapped relative to VHDL. Specifically, I have not done any programming, only reading (quite a lot) trying to understand a little about the subject. Initially Q II (using V9.0) was very challenging so I decided to try out schematic capture and familiarize myself with the megafunctions and this was not a bad idea because Q II itself is no longer a problem (one small hurdle).I have recently muddled my way through the graphical SM tool and was pleased with that. Of course having done such a SM it was quite obvious that I was really working with a VHDL file and that makes sense. So the question became the one I submitted - how can I create a bdf schematic that utilizes the SM. As you now can more fully appreciate I was hoping at this point to avoid detailed VHDL involvement and just work with graphical tools because the VHDL is not easy to get up to speed on (I have little programming experience in my background and am now retirement age). At least I'm not a university student trying to get others to answer my assignment but I still feel embarrassed (:>)). I know that ultimately an HDL is the only way to go for a younger engineer hoping to be useful as an FPGA programmer but I wanted to have some fun learning and using the DE-2 kit without the challenge of fully teaching myself VHDL. So is there any hope for me in my present circumstance? Help in Q II is not much help unless one already has a pretty fair idea what's going on. Thanks for taking the time to give me the initial direction. I recognize the key lies in instantiating another file so that there can be interaction but like I said even that is presently a challenge because of my lack of VHDL experience. I guess this can't be tackled graphically?? Jack
After searching more dilegently I think the solution in my case is to use a bsf so it appears I am once again past a small hurdle without delving into the VHDL. Learning is fun if you don't mind the pain.The SM wizard generates the VHDL which in turn generates a block symbol for connection in a bdf. Jack