How boot from the epcs a multicore system, using de DE0-NANO

[Altera_Forum]

In this moment I am implementing a multicore architecture and my development platform is the DE0-NANO. 

 All the Examples of multicore, come with the architecture using a external flash memory(CFI), but the NANO only has a EPCS Memory.  I want to know..., can I boot a multicore system from the EPCS, using the DE0-NANO?  Do you have any example of multicore, using the NANO and the EPCS? or other similar  Thank you very much.  Best Regards

[Altera_Forum]

I've done it, I've implemented a 4 CPU system in DE0-Nano. There were several challenges: 

 1) First I had to control the reset signal of the "slave" CPUs from CPU0. In my case I had to manuallly modify the VHDL code generated by SOPC builder to be able to use a diferent reset signal for the slave CPUs.  2) I had to do a special bootloader for the slaves CPUs. This bootloader is run in the Master CPU. The bootloader, assert a reset, copy the code stored in flash to the memory of slave CPUs. and then deasserts the reset.  3) The memory location of the slave programs in flash is not obvious, so I had to do a parsing utility that parses the flash files to know the exact code positions. As a consequence the compilation of a new software variation always requires two compilations. The first to apply the functional change, the second to update the code locations.  I think that with QSys it is easier to control the reset signal.