I attached the code for array of pipeline d flipflop please give suggestions to rectify the synthesis error in the code . - Intel Community

Intel® FPGA University Program

University Program Material, Education Boards, and Laboratory Exercises

I attached the code for array of pipeline d flipflop please give suggestions to rectify the synthesis error in the code .

991 Views

29 KB

Link Copied

1 Reply

346 Views

Hi Latha,

Here Net out[2],out[1],out[0] are driving by more than one source & that too direct wiring and that is not recommended, refer the RTL viewer.

If you want to do so you need to write priority logic for corresponding node(like multiplexer).

Regards,

Vikas

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.