I use DSP Builder in Quartus Prime Pro 19.4, When I setup generate hardware option in CONTROL BLOCK， run simulink simulation ， failure is reported

[HBin0]

Error reported by S-function 'mip_control' in 'lms/Control':

Failure to redistribute delay in [lms_Subsystem] - negative cycle

(0) Sub | lms_Subsystem | {  }

(0) Add_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

(0) Add | lms_Subsystem | {  }

(0) Mult_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

(0) Mult_PostCast_primWireOut_rnd_sel | lms_Subsystem | {  }

(-3) Mult_cma | lms_Subsystem | {  }

(1) lms_Subsystem_Subsystem_Add4_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

(0) lms_Subsystem_Subsystem_Add4_x | lms_Subsystem | {  }

(0) lms_Subsystem_Subsystem_Mult5_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

(0) lms_Subsystem_Subsystem_Mult5_PostCast_primWireOut_rnd_x_sel | lms_Subsystem | {  }

(-3) lms_Subsystem_Subsystem_Mult5_x_cma | lms_Subsystem | {  }

(0) Mult4_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

(0) Mult4_PostCast_primWireOut_rnd_sel | lms_Subsystem | {  }

(0) Mult4_shift4 | lms_Subsystem | {  }

(0) Mult4_add_3_BitJoin_for_q | lms_Subsystem | { hintTessellated }

(-1) Mult4_add_3_p1_of_2 | lms_Subsystem | { hintTessellated }

(0) Mult4_add_1 | lms_Subsystem | {  }

(0) Sub_PostCast_primWireOut_sel_x | lms_Subsystem | {  }

[CheePin_C_Intel]

Hi,

As I understand it, you observe some issue when the DSP Builder in Q19.4Pro. For your information, as I try to replicate your observation in my PC, I encounter issue where my Matlab version is older than yours. I only have Matlab 2018b installed in my local PC and unable to open the slx file that you attached. 

Would you mind to help on the following:

1. Please help to elaborate in details on the step to reproduce your observation

2. Just to check with you if this is something can replicated by using any of the example design in DSP Builder? Or only specific to your design?

3. Mind help to export your Model to previous version ie R2018b for me to try opening the file?

4. What is the specific device that you are using?

Thank you very much. 

[HBin0]

I convert my design to R2018b，and send my design to you

[HBin0]

In this design， I use 10CX085YU484E6G FPGA

[CheePin_C_Intel]

Hi,

Thanks for sharing the file. I will look into it and get back to you mid of next week. Please ping me if you do not hear back from me.

[CheePin_C_Intel]

Hi,

Sorry for the delay. I am able to open your design and replicate the error when running Simulink. As I perform further tests, the error seems to be related to your design or algorithm which could potentially cannot be synthesized. As I tested simplifying your subsystem to only simple subtraction, the RTL generation is passing. I am not really a design expert and could not really comment on what might be wrong with your design. You might need to further look into your subsystem and probably add portion by portion to see if can spot any anomaly.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[HBin0]

I find ， if my design have loop path, this error easyly occured , I want to know, what reason will reult in this error? I am writting book about intel fpga to DSP. i think i should tell my reader how to avoid this error ,

[CheePin_C_Intel]

Hi, Thanks for your update. For your information, would you mind to create a test design probably the simplest form ie with single loop path which could replicate the error and share to me. I would like to highlight to Factory to seek further clarification. Thank you very much for your help. Best regards, Chee Pin

[HBin0]

I advice you upload this design to factory， I this the engineer who design DSP Builder can find the reason of error， I estimate it is possible have design rule need to notice， not this design itself。 I think to let all people who use DSP builder know the reason it is most important ，not to try and try agian。

[CheePin_C_Intel]

Hi, Thanks for your update. Just would like to set a correct expectation. Generally Factory will only investigate into a confirmed bug but not potential design related issue. Just would like to check with you if you are seeing expected output from the Matlab simulation? If yes, then I can leverage this to explain to Factory that no issue with simulation and request for their help to look into why HDL generation encounter issue. Thank you very much. Best regards, Chee Pin

[HBin0]

When I don't select generate hdl hardare option, run Simulink simulation , the result is correct。so， you should let Factory help me to find issue.

[CheePin_C_Intel]

Thanks for your clarification. I have file a case to Factory and currently pending for their response. I will keep you posted by early next week or as soon as there is any valid response from them. Please ping me if you do not hear from me.

Thank you.

[CheePin_C_Intel]

Hi,

I have received valid response from Factory. As I understand it, Factory has looked into your design and commented that your subsystem contains a loop with 3 Mult blocks and only 1 Sample Delay of depth=1. Each Mult block has 2 registers irrespective of clock frequency, so you need to have at least depth=6 Sample Delay in that loop.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.